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n u m icro ? dec . 30 , 201 4 page 1 of 97 revision 1.0 1 numicro? numicro? nuc2 30/240 series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro tm microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specification s are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
n u m icro ? dec . 30 , 201 4 page 2 of 97 revision 1.0 1 numicro? table of contents list of figures ................................ ................................ ................................ ..... 6 list of tables ................................ ................................ ................................ ....... 7 1 general description ................................ ................................ ..................... 8 2 features ................................ ................................ ................................ ............ 9 2.1 numicro ? nuc230 features C automotive line ................................ ............ 9 2.2 numicro ? nuc240 features C connectivity line ................................ .......... 13 3 abbreviations ................................ ................................ ................................ 17 4 parts information li st and pin configura tion ................................ 19 4.1 numicro ? nuc230/240xxxae selection guide ................................ ............ 19 4.1.1 numicro ? nuc230 automotive line selection guide ................................ ......... 19 4.1.2 numicro ? nuc240 connectivity line se lection guide ................................ ........ 19 4.2 pin configuration ................................ ................................ ................ 21 4.2.1 numicro ? nuc230 pin diagram ................................ ................................ .. 21 4.2.2 numicro ? nuc240 pin diagram ................................ ................................ .. 24 4.3 pin description ................................ ................................ .................. 27 4.3.1 numicro ? nuc230 pin description ................................ ............................... 27 4.3.2 numicro ? nuc240 pin description ................................ ............................... 35 5 block diagram ................................ ................................ ............................... 43 5.1 numicro ? nuc230 block diagram ................................ ........................... 43 5.2 numicro ? nuc240 block diagram ................................ ........................... 44 6 functional descripti on ................................ ................................ ............. 45 6.1 arm? cortex? - m0 core ................................ ................................ ...... 45 6.2 system manager ................................ ................................ ................ 47 6.2.1 overview ................................ ................................ .............................. 47 6.2.2 system reset ................................ ................................ ........................ 47 6.2.3 syst em power distribution ................................ ................................ ......... 48 6.2.4 system memory map ................................ ................................ ............... 50 6.2.5 system timer (systick) ................................ ................................ ............ 52 6.2.6 nested vectored interrupt controller (nvic) ................................ .................... 53 6.2.7 system control ................................ ................................ ....................... 56 6.3 clock controller ................................ ................................ ................. 57 6.3.1 overview ................................ ................................ .............................. 57 6.3.2 system c lock and systick clock ................................ ................................ . 60
n u m icro ? dec . 30 , 201 4 page 3 of 97 revision 1.0 1 numicro? 6.3.3 power - down mode clock ................................ ................................ ........... 61 6.3.4 frequency divider output ................................ ................................ .......... 62 6.4 flash memory controller (fmc) ................................ .............................. 63 6.4.1 overview ................................ ................................ .............................. 63 6.4.2 features ................................ ................................ .............................. 63 6.5 external bus interface (ebi) ................................ ................................ ... 64 6.5.1 overview ................................ ................................ .............................. 64 6.5.2 features ................................ ................................ .............................. 64 6.6 general purpose i/o (gpio) ................................ ................................ .. 65 6.6.1 overview ................................ ................................ .............................. 65 6.6.2 features ................................ ................................ .............................. 65 6.7 pdma controller (pdma) ................................ ................................ ...... 65 6.7.1 overview ................................ ................................ .............................. 65 6.7.2 features ................................ ................................ .............................. 66 6.8 timer controller (timer) ................................ ................................ ...... 66 6.8.1 overview ................................ ................................ .............................. 66 6.8.2 features ................................ ................................ .............................. 67 6.9 pwm generator and capture timer (pwm) ................................ ................ 68 6.9.1 overview ................................ ................................ .............................. 68 6.9.2 features ................................ ................................ .............................. 69 6.10 watchdog timer (wdt) ................................ ................................ ........ 70 6. 10.1 overview ................................ ................................ .............................. 70 6.10.2 features ................................ ................................ .............................. 70 6.11 window watchdog timer (wwdt) ................................ ........................... 71 6.11.1 overview ................................ ................................ .............................. 71 6.11.2 features ................................ ................................ .............................. 71 6.12 real time clock (rtc) ................................ ................................ ........ 71 6.12.1 overview ................................ ................................ .............................. 71 6.12.2 featu res ................................ ................................ .............................. 71 6.13 uart interface controller (uart) ................................ ........................... 72 6.13.1 overview ................................ ................................ .............................. 72 6.13.2 featu res ................................ ................................ .............................. 72 6.14 smart card host interface (sc) ................................ ............................... 73 6.14.1 overview ................................ ................................ .............................. 73 6.14.2 features ................................ ................................ .............................. 73
n u m icro ? dec . 30 , 201 4 page 4 of 97 revision 1.0 1 numicro? 6.15 ps/2 device controller (ps2d) ................................ ............................... 74 6.15.1 overview ................................ ................................ .............................. 74 6.15.2 features ................................ ................................ .............................. 74 6.16 i 2 c serial interface controller (i 2 c) ................................ ........................... 75 6.16.1 overview ................................ ................................ .............................. 75 6.16.2 features ................................ ................................ .............................. 75 6.17 serial peripheral interface (spi) ................................ .............................. 75 6.17.1 overview ................................ ................................ .............................. 75 6.17.2 features ................................ ................................ .............................. 76 6.18 i 2 s controller (i 2 s) ................................ ................................ .............. 76 6.18.1 overview ................................ ................................ .............................. 76 6.18.2 features ................................ ................................ .............................. 76 6.19 usb device controller (usbd) ................................ ............................... 77 6.19.1 overview ................................ ................................ .............................. 77 6.19.2 features ................................ ................................ .............................. 77 6.20 controller area network (can) ................................ ............................... 78 6.20.1 overview ................................ ................................ .............................. 78 6.20.2 featu res ................................ ................................ .............................. 78 6.21 analog - to - digital converter (adc) ................................ ........................... 78 6.21.1 overview ................................ ................................ .............................. 78 6.21.2 features ................................ ................................ .............................. 78 6.22 analog comparator (acmp) ................................ ................................ ... 79 6.22.1 overview ................................ ................................ .............................. 79 6.22.2 features ................................ ................................ .............................. 79 7 application circuit ................................ ................................ ...................... 80 8 electrical character istics ................................ ................................ .... 81 8.1 absolute maximum ratings ................................ ................................ ... 81 8.2 dc electrical characteristics ................................ ................................ .. 82 8.3 ac electrical characteristics ................................ ................................ .. 87 8.3.1 external 4~24 mhz high speed oscillator ................................ ....................... 87 8.3.2 external 4~24 mhz high speed crystal ................................ .......................... 87 8.3.3 external 32.768 khz low speed crystal oscillat or ................................ ............. 88 8.3.4 internal 22.1184 mhz high speed oscillator ................................ .................... 88 8.3.5 internal 10 khz low speed oscillator ................................ ............................ 88 8.4 analog characteristics ................................ ................................ ......... 89
n u m icro ? dec . 30 , 201 4 page 5 of 97 revision 1.0 1 numicro? 8. 4.1 12 - bit saradc specification ................................ ................................ ...... 89 8.4.2 ldo and power management specification ................................ ..................... 89 8.4.3 low voltage reset specification ................................ ................................ .. 90 8.4.4 brown - out detector specification ................................ ................................ . 90 8.4.5 power - on reset specification ................................ ................................ ..... 90 8.4.6 temperature sensor specification ................................ ................................ 91 8.4.7 comparator specification ................................ ................................ ........... 91 8.4.8 usb phy specification ................................ ................................ ............. 92 8.5 flash dc electrical characteristics ................................ ........................... 93 9 package dimensions ................................ ................................ .................... 94 9.1 100 - pin lqfp (14x14x1.4 mm footprint 2.0 mm) ................................ ........... 94 9.2 64 - pin lqfp (7x7x1.4 mm footprint 2.0 mm) ................................ ............... 95 9.3 48 - pin lqfp (7x7x1.4 mm footprint 2.0 mm) ................................ ............... 96 10 revision history ................................ ................................ ............................ 97
n u m icro ? dec . 30 , 201 4 page 6 of 97 revision 1.0 1 numicro? list of f igures figure 4 - 1 numicro ? nuc230/240 series selection code ................................ ........................... 20 figure 4 - 2 numicro ? nuc230vxxae lqfp 100 - pin diagram ................................ ...................... 21 figure 4 - 3 numicro ? nuc230sxxae lqfp 64 - pin diagram ................................ ........................ 22 figure 4 - 4 numicro ? nuc230lxxae lqfp 48 - pin diagram ................................ ........................ 23 figure 4 - 5 numicro ? nuc240vxxae lqfp 100 - pin diagr am ................................ ...................... 24 figure 4 - 6 numicro ? nuc240sxxae lqfp 64 - pin diagram ................................ ........................ 25 figure 4 - 7 numicro ? nuc240lxxae lqfp 48 - pin diagram ................................ ........................ 26 figure 5 - 1 numicro ? nuc230 block diagram ................................ ................................ .............. 43 figure 5 - 2 numicro ? nuc240 block diagram ................................ ................................ .............. 44 figure 6 - 1 functional controller diagram ................................ ................................ ...................... 45 figure 6 - 2 numicro ? nuc230 power distribution diagram ................................ .......................... 48 figure 6 - 3 numicro ? nuc240 power distribution diagram ................................ .......................... 49 figure 6 - 4 clock generator block diagram ................................ ................................ ................... 58 figure 6 - 5 clock generator global view diagram ................................ ................................ ......... 59 figure 6 - 6 system clock block diagram ................................ ................................ ....................... 60 figure 6 - 7 systick clock control block diagram ................................ ................................ .......... 60 figure 6 - 8 clock source of frequency divider ................................ ................................ .............. 62 figure 6 - 9 frequency divider block diagram ................................ ................................ ................ 62 figure 8 - 1 typical crystal application circuit ................................ ................................ ................ 88
n u m icro ? dec . 30 , 201 4 page 7 of 97 revision 1.0 1 numicro? list of t ables table 1 - 1 numicro ? nuc230/240 series connectivity support table ................................ ........... 8 table 3 - 1 list of abbreviations ................................ ................................ ................................ ....... 18 table 6 - 1 address space assignments for on - chip controllers ................................ ................... 51 table 6 - 2 exception model ................................ ................................ ................................ ............ 54 table 6 - 3 system interrupt map ................................ ................................ ................................ ..... 55 table 6 - 4 vector table format ................................ ................................ ................................ ...... 56
n u m icro ? dec . 30 , 201 4 page 8 of 97 revision 1.0 1 numicro? 1 general description the numicro ? nuc230/240 s eries 32 - bit microcontrollers are embedded with the arm ? cortex? - m0 core with a cost equivalent to traditional 8 - bit mcu for industrial contr ol and applications requiring rich communication interfaces. t he numicro ? nuc230/240 s eries includes nuc 2 3 0 and nuc 2 4 0 product line s . the numicro ? nuc 2 3 0 can line is embed ded with the cortex? - m0 core running up to 72 mhz and features 32k/64k/128k byte s flash, 8k/16k byte s embedded sram, and 8 kbyte s loader rom for the isp. it is also equip ped with plenty of peripheral devices, such as timers, watchdog timer, window watchdog timer, rtc, pdma with crc calculation uni t , uart, spi, i 2 c, i 2 s, pwm timer, gpio, lin, can, ps / 2, smart card host, 12 - bit adc, analog comparator, low voltage reset controller and brown - out detector. the numicro ? nuc 2 4 0 connectivity line with usb 2.0 full - speed and can functions is embed ded with the cortex? - m0 core ru nning up to 72 mhz and features 32k/64k/128k byte s flash, 8k/16k byte s embedded sram, and 8 kbyte s loader rom for the isp. it is also equip ped with plenty of peripheral devices, such as timers, watchdog timer, window watchdog timer, rtc, pdma with crc calc ulation uni t , uart, spi, i 2 c, i 2 s, pwm timer, gpio, lin, can, ps / 2, usb 2.0 fs device, smart card host, 12 - bit adc, analog comparator, low voltage reset controller and brown - out detector. product line uart spi i 2 c usb lin can ps / 2 i 2 s sc nuc 2 3 0 nuc 2 4 0 table 1 - 1 numicro ? nuc230/240 series connectivity support table
n u m icro ? dec . 30 , 201 4 page 9 of 97 revision 1.0 1 numicro? 2 features the equipped features are dependent on the product line and their sub products. 2.1 numicro ? C automotive line ? arm ? cortex? - m0 core C r uns up to 72 mhz C one 24 - bit system timer C supports low power sleep mode C single - cycle 32 - bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4 - levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? buil t - in ldo for wide operating voltage range d from 2.5 v to 5.5 v ? flash memory C 32k/64k/128k bytes flash for program code C 8 kb flash for isp loader C support s in - s ystem - p rogram (isp) and in - application - program (iap) application code update C 512 byte page erase for flash C configurable data flash address and size for 128 kb system, fixed 4 kb data flash for the 32 kb and 64 kb system C support s 2 - wire d icp update through swd/ice interface C su pport s fast parallel programming mode by external programmer ? sram memory C 8k/16k bytes embedded sram C support s pdma mode ? pdma (peripheral dma) C support s 9 channels pdma for automatic data transfer between sram and peripherals C support s crc calculation with fou r common polynomials, crc - ccitt, crc - 8, crc - 16 and crc - 32 ? clock control C flexible selection for different applications C built - in 22.1184 mhz high speed oscillator for system operation ? trimmed to 1 % at +25 and v dd = 5 v ? trimmed to 3 % at - 40 ~ + 10 5 and v dd = 2.5 v ~ 5.5 v C built - in 10 khz low speed oscillator for watchdog timer and wake - up operation C support s one pll, up to 72 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for precise timing operation C external 32 .768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi - bidirection al ? push - p ull output ? open - d rain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin configured as interrupt source with edge/level setting ? timer C support s 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit prescale counter C independent clock source for each timer C provides one - shot, periodic, toggle and continuous counting operation modes C support s event counting function C support s input capture function ? watchdog timer C multiple clock sources
n u m icro ? dec . 30 , 201 4 page 10 of 97 revision 1.0 1 numicro? C 8 selectable time - out period from 1. 6 ms ~ 26 .0 sec (depend ing on clock source) C wake - up from power - down or i dle mode C interrupt or reset selectable on watchdog time - out C supports 4 selectable watchdog timer reset delay period(1026, 130, 18 or 3 wdt_clk) ? window watchdog timer C 6 - bit down counter with 11 - bit prescale for wide range window selected ? rtc C support s software compensation by setting frequency compensate register (fcr) C support s rtc counter (second, minute, hour) and calendar counter (day, month, year) C support s alarm registers (second, minute, hour, day, month, year) C selectable 12 - hour or 24 - hour mode C a utomatic leap year recognition C support s periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C supports battery power pin (vbat ) C support s wake - up function ? pwm/capture C u p to four built - in 16 - bit pwm generators provid ing eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8 - bit prescaler and one dead - zone generator for complementary paired pwm C supports one - shot or auto - reload mode C up to eight 16 - bit digital c apture timers (shared with pwm timers) provid ing eight rising/falling capture inputs C support s capture interrupt ? uart C up to six uart controllers (three uart controllers are shared with sc) C uart ports with flow control (txd, rxd, n cts and n rts) C uart0 with 6 4 - byte fifo is for high speed C uart1/2(optional) with 1 6 - byte fifo for standard device C support s irda (sir) and lin function C support s rs - 485 9 - bit mode and direction control C programmable baud - rate generator up to 1/16 system clock C supports cts wake - up function (uart0 and uart1 support) C support s pdma mode ? smart card host (sc) C support s up to t hree iso - 7816 - 3 ports ? compliant to iso - 7816 - 3 t=0, t=1 ? separate receive / transmit 4 bytes entry fifo for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 266 etu) ? one 24 - bit and two 8 - bit time - out counter s for answer to request (atr) and waiting times processing ? support s auto inverse convention function ? support s transmitter and receiver error retry and error limit function ? support s hardware activation sequence process ? support s hardware warm reset sequence process ? support s hardware deactivation sequence process ? support s hardware auto deactivation sequence when detect ing the card is removal C supports up to three uart ports ? full duplex, asynchronous communications ? supports receiving / transmitting 4 - bytes fifo ? supports programmable baud rate generator for each chann el ? programmable even, odd or no parity bit generation and detection ? programmable stop bit, 1 or 2 stop bit generation
n u m icro ? dec . 30 , 201 4 page 11 of 97 revision 1.0 1 numicro? ? spi C up to four sets of spi controller s C the maximum spi clock rate of master can up to 36 mhz (chip working at 5v) C the maximum spi clock rate of slave can up to 18 mhz (chip working at 5v) C support s spi m aster/ s lave mode C full duplex synchronous serial data transfer C variable length of transfer data from 8 to 32 bit s C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C two slave/device select lines in m aster mode , and one slave/device select line in slave mode C support s b yte s uspend mode in 32 - bit transmission C support s pdma mode C support s three wire, no slave select signal, bi - direction interface ? i 2 c C up to two sets of i 2 c device s C master/slave mode C bidirectional data transfer between masters and slaves C multi - master bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C serial clock synchronization allow ing devices with different bit rates to communicate via one serial bus C serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow ing for versatile rate control C support s multiple address recognition (four slave address with mask option) C support s wake - up function ? i 2 s C interface with external audio codec C operate as either m aster or s lave mode C capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes C supports m ono and stereo audio data C supports i 2 s and msb justified data format C provides t wo 8 word fifo data buffers, one for transmit ting and the other for receiv ing C generates interrupt requests when buffer levels cross a programmable boundary C support s tw o dma requests, one for transmit ting and the other for receiv ing ? ps/2 device C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for da ta reception C s oftware override bus ? can 2.0 C supports can protocol version 2.0 part a and b C bit rates up to 1m bit/s C 32 message objects C each message object has its o wn identifier mask C programmable fifo mode (concatenation of message object) C maskable interrupt C disabled automatic re - transmission mode for time triggered can applications C support wake - up function ? adc C 12 - bit sar adc with 1 msps (chip working at 5v) C up to 8 - ch single - end input or 4 - ch differential input C single scan/single cycle scan/continuous scan
n u m icro ? dec . 30 , 201 4 page 12 of 97 revision 1.0 1 numicro? C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start ed by software programming , external input or pwm center - aligned trigger C support s pdma mode ? analog comparator C up to two a nalog comparator s C external input or internal b and - gap voltage selectable at negative node C interrupt when compare result change C supports power - down wake - up ? ebi (external bus interface) C accessible space: 64 kb in 8 - bit mode or 128 kb in 16 - bit mode C support s 8 - /16 - bit data width C support s byte write in 16 - bit data width mode ? 96 - bit unique id (uid) ? 128 - bit unique customer id(ucid) ? o ne built - in temperature sensor with 1 resolution ? brown - out d etector C with 4 levels: 4. 4 v/3. 7 v/2.7 v/2.2 v C support s brown - out interrupt and reset option ? low voltage reset C threshold voltage level: 2.0 v ? operating temperature: - 40 ~ 10 5 ? packages: C all green package (rohs) C lqfp 100 - pin / 64 - pin / 48 - pin
n u m icro ? dec . 30 , 201 4 page 13 of 97 revision 1.0 1 numicro? 2.2 numicro ? C connectivity line ? arm ? cortex? - m0 core C r uns up to 72 mhz C one 24 - bit system timer C supports low power sleep mode C single - cycle 32 - bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4 - levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? buil t - in ldo for wi de operating voltage ranges from 2.5 v to 5.5 v ? flash memory C 32k/64k/128k bytes flash for program code C 8 kb flash for isp loader C support s in - s ystem - p rogram (isp) and in - application - program (iap) application code update C 512 byte page erase for flash C configu rable data flash address and size for 128 kb system, fixed 4 kb data flash for the 32 kb and 64 kb system C support s 2 - wire d icp update through swd/ice interface ? sram memory C 8k/16k bytes embedded sram C support s pdma mode ? pdma (peripheral dma) C support s 9 channels pdma for automatic data transfer between sram and peripherals C support s crc calculation with four common polynomials, crc - ccitt, crc - 8, crc - 16 and crc - 32 ? clock control C flexible selection for different applications C built - in 22.1184 mhz high speed oscillator for system operation ? trimmed to 1 % at +25 and v dd = 5 v ? trimmed to 3 % at - 40 ~ + 10 5 and v dd = 2.5 v ~ 5.5 v C built - in 10 khz low speed oscillator for watchdog timer and wake - up operation C support s one pll, up to 72 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for usb and precise timing operation C external 32.768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? q uasi - bidirection al ? push - p ull output ? open - d rain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin configured as interrupt source with edge/level setting ? timer C support s 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit prescale counter C independent clock source for each timer C provides one - shot, periodic, toggle and continuous counting operation modes C support s event counting function C support s input capture function ? watchdog timer C multiple clock sources C 8 selectable time - out period from 1. 6 ms ~ 26 .0 sec (depend ing on clock source) C w ake - up from power - down or i dle mode C interrupt or reset selectable on watchdog time - out C supports 4 selectable watchdog timer reset delay period(1026, 130, 18 or 3 wdt_clk)
n u m icro ? dec . 30 , 201 4 page 14 of 97 revision 1.0 1 numicro? ? window watchdog timer C 6 - bit down counter with 11 - bit prescale for wide range window selected ? rtc C support s software compensation by setting frequency compensate register (fcr) C support s rtc counter (second, minute, hour) and calendar counter (day, month, yea r) C support s alarm registers (second, minute, hour, day, month, year) C selectable 12 - hour or 24 - hour mode C automatic leap year recognition C support s periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C supports battery power pin (vbat) C support s wake - up function ? pwm/capture C u p to four built - in 16 - bit pwm generators provid ing eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, on e 8 - bit prescaler and one dead - zone generator for complementary paired pwm C supports one - shot or auto - reload mode C up to eight 16 - bit digital c apture timers (shared with pwm timers) provid ing eight rising/falling capture inputs C support s c apture interrupt ? uar t C up to six uart controllers (three uart controllers are shared with sc) C uart ports with flow control (txd, rxd, n cts and n rts) C uart0 with 6 4 - byte fifo is for high speed C uart1/2(optional) with 1 6 - byte fifo for standard device C support s irda (sir) and lin function C support s rs - 485 9 - bit mode and direction control C programmable baud - rate generator up to 1/16 system clock C supports cts wake - up function (uart0 and uart1 support) C support s pdma mode ? smart card host (sc) C support s up to t hree iso - 7816 - 3 ports ? complia nt to iso - 7816 - 3 t=0, t=1 ? separate receive / transmit 4 bytes entry fifo for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 266 etu) ? one 24 - bit and two 8 - bit time - out counter s for answer to request (atr) and waiting times processing ? support s auto inverse convention function ? support s transmitter and receiver error retry and error limit function ? support s hardware activation sequence process ? support s hardware warm reset sequence process ? support s hardware deactivation sequence process ? support s hardware auto deactivation sequence when detect ing the card is removal C supports up to three uart ports ? full duplex, asynchronous communications ? supports receiving / transmitti ng 4 - bytes fifo ? supports programmable baud rate generator for each channel ? programmable even, odd or no parity bit generation and detection ? programmable stop bit, 1 or 2 stop bit generation ? spi C up to four sets of spi controller s C the maximum spi clock rate of master can up to 36 mhz (chip working at 5v) C the maximum spi clock rate of slave can up to 18 mhz (chip working at 5v)
n u m icro ? dec . 30 , 201 4 page 15 of 97 revision 1.0 1 numicro? C support s spi m aster/ s lave mode C full duplex synchronous serial data transfer C variable length of transfer data from 8 to 32 bit s C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C two slave/device select lines in m aster mode , and one slave/device select line in slave mode C support s b yte s uspend mode in 32 - bit transmission C support s pdma mode C support s three wire, no slave select signal, bi - direction interface ? i 2 c C up to two sets of i 2 c device s C master/slave mode C bidirectional data transfer between masters and slaves C multi - master bus (no central master) C arbitration between simultaneously transmit ting masters without corruption of serial data on the bus C serial clock synchronization allow ing devices with different bit rates to communicate via one serial bus C serial clock synchronization used as a handshake mechanism to suspend and resume serial trans fer C programmable clocks allow ing for versatile rate control C support s multiple address recognition (four slave address with mask option) C support s wake - up function ? i 2 s C interface with external audio codec C operate as either m aster or s lave mode C capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes C supports m ono and s tereo audio data C supports i 2 s and msb justified data format C provides t wo 8 word fifo data buffers, one for transmit ting and the other for receiv ing C generates interrupt requests when buffer leve ls cross a programmable boundary C support s two dma requests, one for transmit ting and the other for receiv ing ? ps/2 device C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C software override bus ? can 2.0 C supports can protocol version 2.0 part a and b C bit rates up to 1m bit/s C 32 message objects C each message object has its o w n identifier mask C programmable fifo mode (concat enation of message object) C maskable interrupt C disabled automatic re - transmission mode for time triggered can applications C support s power - down wake - up function ? usb 2.0 full - speed device C one set of usb 2.0 fs device 12 mbps C on - chip usb transceiver C provide s 1 interrupt source with 4 interrupt events C support s control, bulk in/out, interrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms C provide s 8 programmable endpoints C include s 512 bytes internal sram as usb buffer
n u m icro ? dec . 30 , 201 4 page 16 of 97 revision 1.0 1 numicro? C provide s remote wake - up capability ? adc C 12 - bit sar adc with 1 msps(chip working at 5v) C up to 8 - ch single - end input or 4 - ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C thresh old voltage detection C conversion start ed by software programming , external input or pwm center - aligned trigger C support s pdma m ode ? analog comparator C up to two analog comparator s C external input or internal b and - gap voltage selectable at negative node C interru pt when compare result change C support s power - down wake - up ? ebi (external bus interface) C accessible space: 64 kb in 8 - bit mode or 128 kb in 16 - bit mode C support s 8 - /16 - bit data width C support s byte write in 16 - bit data width mode ? 96 - bit unique id (uid) ? 128 - bit unique customer id(ucid) ? one built - in temperature sensor with 1 resolution ? brown - out d etector C with 4 levels: 4. 4 v/3. 7 v/2.7 v/2.2 v C support s brown - out interrupt and reset option ? low voltage reset C threshold voltage level: 2.0 v ? operating temperature: - 40 ~ 10 5 ? packages: C all green package (rohs) C lqfp 100 - pin / 64 - pin / 48 - pin
n u m icro ? dec . 30 , 201 4 page 17 of 97 revision 1.0 1 numicro? 3 abbreviations acronym description acmp analog comparator controller adc analog - to - digital converter aes advanced encryption standard apb advanced peripheral bus ahb a dvanced h igh - p erforman ce b us bod brown - out detection can controller area network dap debug access port des data encryption standard ebi external bus interface epwm enhanced pulse width modulation fifo first in, first out fmc flash memory controller fpu floating - point unit gpio general - purpose input/output hclk the clock of a dvanced h igh - p erformance b us hirc 22.1184 mhz i nternal h igh s peed rc o scillator hxt 4~24 mhz e xternal h igh s peed c rystal o scillator iap in application programming icp in circuit programming isp in system programming ldo low dropout regulator lin local interconnect network lirc 10 khz internal low speed rc oscillator (lirc) mpu memory protection unit nvic nested vectored interrupt controller pclk the clock of advanced peripheral bus pdma peripheral direct memory access pll phase - locked loop pwm pulse width modulation qei quadrature encoder interface sdio secure digital input/output spi serial peripheral interface
n u m icro ? dec . 30 , 201 4 page 18 of 97 revision 1.0 1 numicro? sps samples per second tdes triple data encryption standard tmr timer controller uart universal asynchronous receiver/transmitter ucid unique customer id usb universal serial bus wdt watchdog timer wwdt window watchdog timer table 3 - 1 list of abbreviations
n u m icro ? dec . 30 , 201 4 page 19 of 97 revision 1.0 1 numicro? 4 parts information li st and pin configura tion 4.1 numicro ? 4.1.1 numicro ? part n umber aprom ( kb ) ram ( kb ) data flash ( kb ) isp rom ( kb ) i/o timer (3 2 - b it ) connectivity i 2 s sc comp. pwm adc (1 2 - b it ) rtc ebi isp / icp /iap package uart spi i 2 c usb lin can nuc 23 0l c2ae 32 8 4 8 3 5 4 5 1 2 - 3 2 1 2 1 4 7 v - v lqfp48 nuc 23 0ld 2ae 64 8 4 8 3 5 4 5 1 2 - 3 2 1 2 1 4 7 v - v lqfp48 nuc 23 0le3 ae 128 16 config . 8 3 5 4 5 1 2 - 3 2 1 2 1 4 7 v - v lqfp48 nuc 23 0 sc2ae 32 8 4 8 4 9 4 5 2 2 - 3 2 1 2 2 6 7 v v v lqfp64 nuc 23 0 sd2ae 64 8 4 8 4 9 4 5 2 2 - 3 2 1 2 2 6 7 v v v lqfp64 nuc 23 0 se3ae 128 16 config . 8 4 9 4 5 2 2 - 3 2 1 2 2 6 7 v v v lqfp64 nuc 23 0ve3 ae 128 16 config . 8 83 4 6 4 2 - 3 2 1 3 2 8 8 v v v lqfp100 4.1.2 numicro ? part n umber aprom ( kb ) ram ( kb ) data flash ( kb ) isp rom ( kb ) i/o timer (3 2 - b it ) connectivity i 2 s sc comp. pwm adc (1 2 - b it ) rtc ebi isp / icp /iap package uart spi i 2 c usb lin can nuc 24 0l c2ae 32 8 4 8 31 4 4 1 2 1 2 2 1 1 1 4 7 v - v lqfp48 nuc 24 0ld 2ae 64 8 4 8 31 4 4 1 2 1 2 2 1 1 1 4 7 v - v lqfp48 nuc 24 0le3 ae 128 16 config . 8 31 4 4 1 2 1 2 2 1 1 1 4 7 v - v lqfp48 nuc 24 0 sc2ae 32 8 4 8 45 4 5 2 2 1 3 2 1 2 2 4 7 v v v lqfp64 nuc 24 0 sd2ae 64 8 4 8 45 4 5 2 2 1 3 2 1 2 2 4 7 v v v lqfp64 nuc 24 0 se3ae 128 16 config . 8 45 4 5 2 2 1 3 2 1 2 2 4 7 v v v lqfp64 nuc 24 0ve3 ae 128 16 config . 8 7 9 4 6 4 2 1 3 2 1 3 2 8 8 v v v lqfp100
n u m icro ? dec . 30 , 201 4 page 20 of 97 revision 1.0 1 numicro? figure 4 - 1 numicro ? nuc230/240 series s election c ode n u c 2 x - x x a r m - b a s e d 3 2 - b i t m i c r o c o n t r o l l e r 3 : a u t o m o t i v e l i n e 4 : c o n n e c t i v i t y l i n e c p u c o r e 1 / 2 : c o r t e x - m 0 5 / 7 : a r m 7 9 : a r m 9 t e m p e r a t u r e n : - 4 0 r e s e r v e x x f u n c t i o n 0 p a c k a g e t y p e l : l q f p 4 8 s : l q f p 6 4 v : l q f p 1 0 0 x r a m s i z e 2 : 8 k b 3 : 1 6 k b a p r o m s i z e c : 3 2 k b d : 6 4 k b e : 1 2 8 k b
n u m icro ? dec . 30 , 201 4 page 21 of 97 revision 1.0 1 numicro? 4.2 pin configuration 4.2.1 numicro ? 4.2.1.1 numicro ? nuc 23 0vxxae lqfp 100 pin figure 4 - 2 numicro ? nuc 23 0v xxae lqfp 100 - pin diagram s c 1 _ r s t / a d 8 / a d c 5 / p a . 5 u a r t 4 _ t x d / s c 1 _ c l k / a d 7 / a d c 6 / p a . 6 u a r t 4 _ r x d / s c 1 _ d a t / a d 6 / a d c 7 / s p i 2 _ s s 1 / p a . 7 a d 0 / s p i 3 _ s s 1 / i n t 0 / p b . 1 4 a d 1 / a c m p 1 _ o / p b . 1 3 v b a t x 3 2 _ i n x 3 2 _ o u t n r d / c a n 1 _ r x d / i 2 c 1 _ s c l / p a . 1 1 n w r / c a n 1 _ t x d / i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 a l e / u a r t 1 _ n r t s / p b . 6 n c s / u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s s c 1 _ c d / a d 5 / a c m p 0 _ n / p c . 7 s c 0 _ c d / a d 4 / a c m p 0 _ p / p c . 6 a d 3 / a c m p 1 _ n / p c . 1 5 a d 2 / a c m p 1 _ p / p c . 1 4 t m 0 / t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / s c 1 _ p w r / a d 9 p a . 3 / a d c 3 / s c 0 _ d a t / u a r t 3 _ r x d / a d 1 0 p a . 2 / a d c 2 / s c 0 _ c l k / u a r t 3 _ t x d / a d 1 1 p a . 1 / a d c 1 / s c 0 _ r s t / a d 1 2 p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t / u a r t 5 _ r x d / a d 1 3 p a . 1 3 / p w m 1 / s c 2 _ c l k / u a r t 5 _ t x d / a d 1 4 p a . 1 4 / p w m 2 / s c 2 _ r s t / a d 1 5 p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r p c . 8 / s p i 1 _ s s 0 / m c l k p c . 9 / s p i 1 _ c l k a v d d v s s v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o p d . 1 5 / u a r t 2 _ t x d / c a n 1 _ t x d p d . 1 4 / u a r t 2 _ r x d / c a n 1 _ r x d p d . 7 / c a n 0 _ t x d p d . 6 / c a n 0 _ r x d p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d / t m 3 / n w r h p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / a c m p 0 _ o / t m 2 / n w r l p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d p e . 7 p e . 8 p e . 9 p e . 1 0 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 n u c 2 3 0 v x x a e l q f p 1 0 0 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p e . 1 5 p e . 1 4 p e . 1 3 s p i 3 _ s s 0 / p d . 8 s p i 3 _ c l k / p d . 9 s p i 3 _ m i s o 0 / p d . 1 0 s p i 3 _ m o s i 0 / p d . 1 1 s p i 3 _ m i s o 1 / p d . 1 2 s p i 3 _ m o s i 1 / p d . 1 3 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p e . 1 1 p e . 1 2 p c . 4 / s p i 0 _ m i s o 1 p c . 5 / s p i 0 _ m o s i 1 p b . 9 / t m 1 / s p i 1 _ s s 1 p b . 1 0 / t m 2 / s p i 0 _ s s 1 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t m 1 _ e x t / p w m 5 / t m 1 p e . 6 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 v s s v d d p c . 1 2 / s p i 1 _ m i s o 1 p c . 1 3 / s p i 1 _ m o s i 1 p e . 0 / p w m 6 p e . 1 / p w m 7 p e . 2 p e . 3 p e . 4 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 p s 2 _ d a t / p f . 2 p s 2 _ c l k / p f . 3 s p i 2 _ s s 0 / p d . 0 s p i 2 _ c l k / p d . 1 s p i 2 _ m i s o 0 / p d . 2 s p i 2 _ m o s i 0 / p d . 3 s p i 2 _ m i s o 1 / p d . 4 s p i 2 _ m o s i 1 / p d . 5 v r e f
n u m icro ? dec . 30 , 201 4 page 22 of 97 revision 1.0 1 numicro? 4.2.1.2 numicro ? nuc 23 0 s xxae lqfp 64 pin figure 4 - 3 numicro ? nuc 23 0 s xxae lqfp 64 - pin diagram a d 8 / a d c 5 / p a . 5 a d 7 / a d c 6 / p a . 6 v r e f a d 0 / i n t 0 / p b . 1 4 a d 1 / a c m p 1 _ o / p b . 1 3 v b a t x 3 2 _ i n x 3 2 _ o u t n r d / c a n 1 _ r x d / i 2 c 1 _ s c l / p a . 1 1 n w r / c a n 1 _ t x d / i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 a l e / u a r t 1 _ n r t s / p b . 6 n c s / u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s a d 5 / a c m p 0 _ n / p c . 7 s c 0 _ c d / a d 4 / a c m p 0 _ p / p c . 6 a d 3 / a c m p 1 _ n / p c . 1 5 a d 2 / a c m p 1 _ p / p c . 1 4 a d 6 / t m 0 / t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / a d 9 p a . 3 / a d c 3 / s c 0 _ d a t / u a r t 3 _ r x d / a d 1 0 p a . 2 / a d c 2 / s c 0 _ c l k / u a r t 3 _ t x d / a d 1 1 p a . 1 / a d c 1 / s c 0 _ r s t / a d 1 2 p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t / u a r t 5 _ r x d / a d 1 3 p a . 1 3 / p w m 1 / s c 2 _ c l k / u a r t 5 _ t x d / a d 1 4 p a . 1 4 / p w m 2 / s c 2 _ r s t / a d 1 5 p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r p c . 8 / s p i 1 _ s s 0 / m c l k p c . 9 / s p i 1 _ c l k a v d d v s s v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o p d . 1 5 / u a r t 2 _ t x d / c a n 1 _ t x d p d . 1 4 / u a r t 2 _ r x d / c a n 1 _ r x d p d . 7 / c a n 0 _ t x d p d . 6 / c a n 0 _ r x d p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d / t m 3 / n w r h p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / a c m p 0 _ o / t m 2 / n w r l p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 p b . 9 / t m 1 p b . 1 0 / t m 2 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t m 1 _ e x t / p w m 5 / t m 1 n u c 2 3 0 s x x a e l q f p 6 4 - p i n
n u m icro ? dec . 30 , 201 4 page 23 of 97 revision 1.0 1 numicro? 4.2.1.3 numicro ? nuc 23 0 l xxae lqfp 48 pin figure 4 - 4 numicro ? nuc 23 0l xxae lqfp 48 - pin diagram a d c 5 / p a . 5 a d c 6 / p a . 6 v r e f v b a t x 3 2 _ i n x 3 2 _ o u t c a n 1 _ r x d / i 2 c 1 _ s c l / p a . 1 1 c a n 1 _ t x d / i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 l d o _ c a p v d d v s s a c m p 0 _ n / p c . 7 s c 0 _ c d / a c m p 0 _ p / p c . 6 t m 0 / t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 p a . 3 / a d c 3 / s c 0 _ d a t / u a r t 3 _ r x d p a . 2 / a d c 2 / s c 0 _ c l k / u a r t 3 _ t x d p a . 1 / a d c 1 / s c 0 _ r s t p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t / u a r t 5 _ r x d p a . 1 3 / p w m 1 / s c 2 _ c l k / u a r t 5 _ t x d p a . 1 4 / p w m 2 / s c 2 _ r s t p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r a v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o p d . 7 / c a n 0 _ t x d p d . 6 / c a n 0 _ r x d p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d / t m 3 p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / a c m p 0 _ o / t m 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n u c 2 3 0 l x x a e l q f p 4 8 - p i n p d . 1 5 / u a r t 2 _ t x d / c a n 1 _ t x d p d . 1 4 / u a r t 2 _ r x d / c a n 1 _ r x d p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d
n u m icro ? dec . 30 , 201 4 page 24 of 97 revision 1.0 1 numicro? 4.2.2 numicro ? 4.2.2.1 numicro ? nuc 24 0 v xxae lqfp 100 pin figure 4 - 5 numicro ? nuc 24 0v xxae lqfp 100 - pin diagram s c 1 _ r s t / a d 8 / a d c 5 / p a . 5 u a r t 4 _ t x d / s c 1 _ c l k / a d 7 / a d c 6 / p a . 6 u a r t 4 _ r x d / s c 1 _ d a t / a d 6 / a d c 7 / s p i 2 _ s s 1 / p a . 7 a d 0 / s p i 3 _ s s 1 / i n t 0 / p b . 1 4 a d 1 / a c m p 1 _ o / p b . 1 3 v b a t x 3 2 _ i n x 3 2 _ o u t n r d / c a n 1 _ r x d / i 2 c 1 _ s c l / p a . 1 1 n w r / c a n 1 _ t x d / i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 a l e / u a r t 1 _ n r t s / p b . 6 n c s / u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s s c 1 _ c d / a d 5 / a c m p 0 _ n / p c . 7 s c 0 _ c d / a d 4 / a c m p 0 _ p / p c . 6 a d 3 / a c m p 1 _ n / p c . 1 5 a d 2 / a c m p 1 _ p / p c . 1 4 t m 0 / t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / s c 1 _ p w r / a d 9 p a . 3 / a d c 3 / s c 0 _ d a t / u a r t 3 _ r x d / a d 1 0 p a . 2 / a d c 2 / s c 0 _ c l k / u a r t 3 _ t x d / a d 1 1 p a . 1 / a d c 1 / s c 0 _ r s t / a d 1 2 p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t / u a r t 5 _ r x d / a d 1 3 p a . 1 3 / p w m 1 / s c 2 _ c l k / u a r t 5 _ t x d / a d 1 4 p a . 1 4 / p w m 2 / s c 2 _ r s t / a d 1 5 p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r p c . 8 / s p i 1 _ s s 0 / m c l k p c . 9 / s p i 1 _ c l k a v d d v s s v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o p d . 1 5 / u a r t 2 _ t x d / c a n 1 _ t x d p d . 1 4 / u a r t 2 _ r x d / c a n 1 _ r x d p d . 7 / c a n 0 _ t x d p d . 6 / c a n 0 _ r x d p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d / t m 3 / n w r h p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / a c m p 0 _ o / t m 2 / n w r l p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 n u c 2 4 0 v x x a e l q f p 1 0 0 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p e . 1 5 p e . 1 4 p e . 1 3 s p i 3 _ s s 0 / p d . 8 s p i 3 _ c l k / p d . 9 s p i 3 _ m i s o 0 / p d . 1 0 s p i 3 _ m o s i 0 / p d . 1 1 s p i 3 _ m i s o 1 / p d . 1 2 s p i 3 _ m o s i 1 / p d . 1 3 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p e . 7 p e . 8 p c . 4 / s p i 0 _ m i s o 1 p c . 5 / s p i 0 _ m o s i 1 p b . 9 / t m 1 / s p i 1 _ s s 1 p b . 1 0 / t m 2 / s p i 0 _ s s 1 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t m 1 _ e x t / p w m 5 / t m 1 p e . 6 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 v s s v d d p c . 1 2 / s p i 1 _ m i s o 1 p c . 1 3 / s p i 1 _ m o s i 1 p e . 0 / p w m 6 p e . 1 / p w m 7 p e . 2 p e . 3 p e . 4 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 p s 2 _ d a t / p f . 2 p s 2 _ c l k / p f . 3 s p i 2 _ s s 0 / p d . 0 s p i 2 _ c l k / p d . 1 s p i 2 _ m i s o 0 / p d . 2 s p i 2 _ m o s i 0 / p d . 3 s p i 2 _ m i s o 1 / p d . 4 s p i 2 _ m o s i 1 / p d . 5 v r e f
n u m icro ? dec . 30 , 201 4 page 25 of 97 revision 1.0 1 numicro? 4.2.2.2 numicro ? nuc 24 0 s xxae lqfp 64 pin figure 4 - 6 numicro ? nuc 24 0 s xxae lqfp 64 - pin diagram a d 8 / a d c 5 / p a . 5 a d 7 / a d c 6 / p a . 6 v r e f a d 0 / i n t 0 / p b . 1 4 a d 1 / a c m p 1 _ o / p b . 1 3 v b a t x 3 2 _ i n x 3 2 _ o u t n r d / c a n 1 _ r x d / i 2 c 1 _ s c l / p a . 1 1 n w r / c a n 1 _ t x d / i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 a l e / u a r t 1 _ n r t s / p b . 6 n c s / u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s a d 5 / a c m p 0 _ n / p c . 7 s c 0 _ c d / a d 4 / a c m p 0 _ p / p c . 6 a d 3 / a c m p 1 _ n / p c . 1 5 a d 2 / a c m p 1 _ p / p c . 1 4 a d 6 / t m 0 / t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / a d 9 p a . 3 / a d c 3 / s c 0 _ d a t / u a r t 3 _ r x d / a d 1 0 p a . 2 / a d c 2 / s c 0 _ c l k / u a r t 3 _ t x d / a d 1 1 p a . 1 / a d c 1 / s c 0 _ r s t / a d 1 2 p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t / u a r t 5 _ r x d / a d 1 3 p a . 1 3 / p w m 1 / s c 2 _ c l k / u a r t 5 _ t x d / a d 1 4 p a . 1 4 / p w m 2 / s c 2 _ r s t / a d 1 5 p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r p c . 8 / s p i 1 _ s s 0 / m c l k p c . 9 / s p i 1 _ c l k a v d d v s s v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o p d . 1 5 / u a r t 2 _ t x d / c a n 1 _ t x d p d . 1 4 / u a r t 2 _ r x d / c a n 1 _ r x d p d . 7 / c a n 0 _ t x d p d . 6 / c a n 0 _ r x d p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d / t m 3 / n w r h p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / a c m p 0 _ o / t m 2 / n w r l p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 n u c 2 4 0 s x x a e l q f p 6 4 - p i n
n u m icro ? dec . 30 , 201 4 page 26 of 97 revision 1.0 1 numicro? 4.2.2.3 numicro ? nuc 24 0 l xxae lqfp 48 pin figure 4 - 7 numicro ? nuc 24 0l xxae lqfp 48 - pin diagram a d c 5 / p a . 5 a d c 6 / p a . 6 v r e f v b a t x 3 2 _ i n x 3 2 _ o u t c a n 1 _ r x d / i 2 c 1 _ s c l / p a . 1 1 c a n 1 _ t x d / i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 l d o _ c a p v d d v s s a c m p 0 _ n / p c . 7 s c 0 _ c d / a c m p 0 _ p / p c . 6 t m 0 / t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 p a . 3 / a d c 3 / s c 0 _ d a t / u a r t 3 _ r x d p a . 2 / a d c 2 / s c 0 _ c l k / u a r t 3 _ t x d p a . 1 / a d c 1 / s c 0 _ r s t p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / u a r t 5 _ r x d p a . 1 3 / p w m 1 / u a r t 5 _ t x d p a . 1 4 / p w m 2 p a . 1 5 / p w m 3 / i 2 s _ m c l k a v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c l k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o p d . 7 / c a n 0 _ t x d p d . 6 / c a n 0 _ r x d p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n u c 2 4 0 l x x a e l q f p 4 8 - p i n
n u m icro ? dec . 30 , 201 4 page 27 of 97 revision 1.0 1 numicro? 4.3 pin description 4.3.1 numicro ? pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 1 pe.15 i/o general purpose digital i/o pin. 2 pe.14 i/o general purpose digital i/o pin. 3 pe.13 i/o general purpose digital i/o pin. 4 1 pb.14 i/o general purpose digital i/o pin. ad0 i/o ebi address/data bus bit0 int0 i external interrupt 0 input pin . spi3_ ss1 i/o 2 nd spi3 slave select pin . 5 2 pb.13 i/o general purpose digital i/o pin. ad1 i/o ebi address/data bus bit1 a c m p 1_ o o comparator1 output pin . 6 3 1 v bat p power supply by batteries for rtc. 7 4 2 x32 _ o ut o external 32.768 khz ( low speed ) crystal output pin . 8 5 3 x32 _ i n i external 32.768 khz ( low speed ) crystal input pin . 9 6 4 pa.11 i/o general purpose digital i/o pin. i2c1 _ scl i/o i 2 c1 clock pin . can1_rxd i data receiver input pin for can1. nrd o ebi read enable output pin 10 7 5 pa.10 i/o general purpose digital i/o pin. i2c1 _ sda i/o i 2 c1 data input/output pin . can1_txd o data transmitter output pin for can1. nwr o ebi write enable output pin 11 8 6 pa.9 i/o general purpose digital i/o pin. i2c0 _ scl i/o i 2 c0 clock pin . 12 9 7 pa.8 i/o general purpose digital i/o pin. i2c0 _ sda i/o i 2 c0 data input/output pin . 13 pd.8 i/o general purpose digital i/o pin. spi3_ ss0 i/o 1 st spi3 slave select pin . 14 pd.9 i/o general purpose digital i/o pin. spi3_ clk i/o spi3 serial clock pin . 15 pd.10 i/o general purpose digital i/o pin.
n u m icro ? dec . 30 , 201 4 page 28 of 97 revision 1.0 1 numicro? pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin spi3_ miso0 i/o 1 st spi3 miso (master in, slave out) pin . 16 pd.11 i/o general purpose digital i/o pin. spi3_ mosi0 i/o 1 st spi3 mosi (master out, slave in) pin . 17 pd.12 i/o general purpose digital i/o pin. spi3_ miso1 i/o 2 nd spi3 miso (master in, slave out) pin . 18 pd.13 i/o general purpose digital i/o pin. spi3_ mosi1 i/o 2 nd spi3 mosi (master out, slave in) pin . 19 10 8 pb.4 i/o general purpose digital i/o pin. uart1_ rxd i data receiver input pin for uart1 . 20 11 9 pb.5 i/o general purpose digital i/o pin. uart1_ txd o data transmitter output pin for uart1 . 21 12 pb.6 i/o general purpose digital i/o pin. ale o ebi address latch enable output pin uart1_n rts o request to send output pin for uart1 . 22 13 pb.7 i/o general purpose digital i/o pin. ncs o ebi chip select enable output pin uart1_n cts i clear to send input pin for uart1 . 23 14 10 ldo _cap p ldo output pin . 24 15 11 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 25 16 12 v ss p ground pin for digital circuit. 26 pe.12 i/o general purpose digital i/o pin. 27 pe.11 i/o general purpose digital i/o pin. 28 pe.10 i/o general purpose digital i/o pin. 29 pe.9 i/o general purpose digital i/o pin. 30 pe.8 i/o general purpose digital i/o pin. 31 pe.7 i/o general purpose digital i/o pin. 32 17 13 pb.0 i/o general purpose digital i/o pin. uart0_ rxd i data receiver input pin for uart0 . 33 18 14 pb.1 i/o general purpose digital i/o pin. uart0_ txd o data transmitter output pin for uart0 . 34 19 15 pb.2 i/o general purpose digital i/o pin. uart0_n rts o request to send output pin for uart0 .
n u m icro ? dec . 30 , 201 4 page 29 of 97 revision 1.0 1 numicro? pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin t m 2 _ ex t i timer2 external capture input pin . a cmp0_o o comparator0 output pin. nwrl o ebi low byte write enable output pin 35 20 16 pb.3 i/o general purpose digital i/o pin. uart0_n cts i clear to send input pin for uart0 . t m 3 _ ex t i timer3 external capture input pin . sc2_cd i smartcard 2 card detect pin . nwrh o ebi high byte write enable output pin 36 21 17 pd.6 i/o general purpose digital i/o pin. can0_rxd i data receiver input pin for can0. 37 22 18 pd.7 i/o general purpose digital i/o pin. can0_txd o data transmitter output pin for can0. 38 23 19 pd.14 i/o general purpose digital i/o pin. uart2_ rxd i data receiver input pin for uart2 . can1_rxd i data receiver input pin for can1. 39 24 20 pd.15 i/o general purpose digital i/o pin. uart2_ txd o data transmitter output pin for uart2 . can1_txd o data transmitter output pin for can1. 40 pc.5 i/o general purpose digital i/o pin. spi0_ mosi1 i/o 2 nd spi0 mosi (master out, slave in) pin . 41 pc.4 i/o general purpose digital i/o pin. spi0_ miso1 i/o 2 nd spi0 miso (master in, slave out) pin . 42 25 21 pc.3 i/o general purpose digital i/o pin. spi0_ mosi0 i/o 1 st spi0 mosi (master out, slave in) pin . i2s _ do o i 2 s data output . 43 26 22 pc.2 i/o general purpose digital i/o pin. spi0_ miso0 i/o 1 st spi0 miso (master in, slave out) pin . i2s _ di i i 2 s data input . 44 27 23 pc.1 i/o general purpose digital i/o pin. spi0_ clk i/o spi0 serial clock pin . i2s _ bclk i/o i 2 s bit clock pin . 45 28 24 pc.0 i/o general purpose digital i/o pin.
n u m icro ? dec . 30 , 201 4 page 30 of 97 revision 1.0 1 numicro? pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin spi0_ ss0 i/o 1 st spi0 slave select pin . i2s _ lrc l k i/o i 2 s left right channel clock . 46 pe.6 i/o general purpose digital i/o pin. 47 29 pe.5 i/o general purpose digital i/o pin. pwm5 i/o pwm 5 output/capture input . t m 1 _ ex t i timer1 external capture input pin. tm 1 o timer 1 toggle output pin. 48 30 pb.11 i/o general purpose digital i/o pin. tm3 i/o timer3 event counter input / toggle output . pwm4 i/o pwm 4 output/capture input . 49 31 pb.10 i/o general purpose digital i/o pin. tm2 i/o timer2 event counter input / toggle output . spi0_ ss1 i/o 2 nd spi0 slave select pin . 50 32 pb.9 i/o general purpose digital i/o pin. tm1 i/o timer1 event counter input / toggle output . spi1_ ss1 i/o 2 nd spi1 slave select pin . 51 pe.4 i/o general purpose digital i/o pin. 52 pe.3 i/o general purpose digital i/o pin. 53 pe.2 i/o general purpose digital i/o pin. 54 pe.1 i/o general purpose digital i/o pin. pwm7 i/o pwm 7 output/capture input . 55 pe.0 i/o general purpose digital i/o pin . pwm6 i/o pwm 6 output/capture input . 56 pc.13 i/o general purpose digital i/o pin. spi1_ mosi1 i/o 2 nd spi1 mosi (master out, slave in) pin . 57 pc.12 i/o general purpose digital i/o pin. spi1_ miso1 i/o 2 nd spi1 miso (master in, slave out) pin . 58 33 pc.11 i/o general purpose digital i/o pin. spi1_ mosi0 i/o 1 st spi1 mosi (master out, slave in) pin . 59 34 pc.10 i/o general purpose digital i/o pin. spi1_ miso0 i/o 1 st spi1 miso (master in, slave out) pin . 60 35 pc.9 i/o general purpose digital i/o pin.
n u m icro ? dec . 30 , 201 4 page 31 of 97 revision 1.0 1 numicro? pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin spi1_ clk i/o spi1 serial clock pin . 61 36 pc.8 i/o general purpose digital i/o pin. mclk o ebi clock output spi1_ ss0 i/o 1 st spi1 slave select pin . 62 37 25 pa.15 i/o general purpose digital i/o pin. pwm3 i/o pwm output/capture input . i2s _ mclk o i 2 s master clock output pin . sc2_pwr o smartcard 2 power pin . 63 38 26 pa.14 i/o general purpose digital i/o pin. pwm2 i/o pwm 2 output/capture input . sc2_rst o smartcard 2 reset pin . ad15 i/o ebi address/data bus bit15 64 39 27 pa.13 i/o general purpose digital i/o pin. pwm1 i/o pwm 1 output/capture input . sc2_clk o smartcard 2 clock pin . uart5_txd o data transmitter output pin for uart 5. ad14 i/o ebi address/data bus bit14 65 40 28 pa.12 i/o general purpose digital i/o pin. pwm0 i/o pwm 0 output/capture input . sc2_dat o smartcard 2 data pin . uart5_rxd i data receiver input pin for uart 5. ad13 i/o ebi address/data bus bit13 66 41 29 ice_dat i/o serial w ire d ebugger d ata pin . 67 42 30 ice_c l k i serial w ire d ebugger c lock pin . 68 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 69 v ss p ground pin for digital circuit. 70 43 31 av ss ap ground p in for analog circuit . 71 44 32 pa.0 i/o general purpose digital i/o pin. adc0 ai adc 0 analog input . sc0_pwr o smartcard 0 power pin . 72 45 33 pa.1 i/o general purpose digital i/o pin. adc1 ai adc 1 analog input .
n u m icro ? dec . 30 , 201 4 page 32 of 97 revision 1.0 1 numicro? pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin sc0_rst o smartcard 0 reset pin . ad12 i/o ebi address/data bus bit12 73 46 34 pa.2 i/o general purpose digital i/o pin. adc2 ai adc 2 analog input . sc0_clk o smartcard 0 clock pin . uart3_txd o data transmitter output pin for uart 3. ad11 i/o ebi address/data bus bit11 74 47 35 pa.3 i/o general purpose digital i/o pin. adc3 ai adc 3 analog input . sc0_dat o smartcard 0 data pin . uart3_rxd i data receiver input pin for uart 3. ad10 i/o ebi address/data bus bit10 75 48 36 pa.4 i/o general purpose digital i/o pin. adc4 ai adc 4 analog input . ad9 i/o ebi address/data bus bit9 sc1 _pwr o smartcard1 power pin . 76 49 37 pa.5 i/o general purpose digital i/o pin. adc5 ai adc5 analog input. ad8 i/o ebi address/data bus bit8 sc1 _rst o smartcard1 reset pin . 77 50 38 pa.6 i/o general purpose digital i/o pin. adc6 ai adc 6 analog input . ad7 i/o ebi address/data bus bit7 sc1 _clk i/o smartcard1 clock pin . uart4_txd o data transmitter output pin for uart 4. 78 pa.7 i/o general purpose digital i/o pin. adc7 ai adc 7 analog input . ad6 i/o ebi address/data bus bit6 sc1 _dat o smartcard1 data pin . uart4_rxd i data receiver input pin for uart 4. spi2_ ss1 i/o 2 nd spi2 slave select pin . 79 51 39 v ref ap voltage reference input for adc . 80 52 40 av dd ap power supply for internal analog circuit .
n u m icro ? dec . 30 , 201 4 page 33 of 97 revision 1.0 1 numicro? pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 81 pd.0 i/o general purpose digital i/o pin. spi2_ ss0 i/o 1 st spi2 slave select pin . 82 pd.1 i/o general purpose digital i/o pin. spi2_ clk i/o spi2 serial clock pin . 83 pd.2 i/o general purpose digital i/o pin. spi2_ miso0 i/o 1 st spi2 miso (master in, slave out) pin . 84 pd.3 i/o general purpose digital i/o pin. spi2_ mosi0 i/o 1 st spi2 mosi (master out, slave in) pin . 85 pd.4 i/o general purpose digital i/o pin. spi2_ miso1 i/o 2 nd spi2 miso (master in, slave out) pin . 86 pd.5 i/o general purpose digital i/o pin. spi2_ mosi1 i/o 2 nd spi2 mosi (master out, slave in) pin . 87 53 41 pc.7 i/o general purpose digital i/o pin. c m p 0_ n ai comparator0 n egative input pin . ad5 i/o ebi address/data bus bit5 sc1 _ cd i smartcard1 card detect pin . 88 54 42 pc.6 i/o general purpose digital i/o pin. a c m p 0_ p ai comparator0 p ositive input pin . sc 0_ cd i smartcard 0 card detect pin . ad4 i/o ebi address/data bus bit4 89 55 pc.15 i/o general purpose digital i/o pin. ad3 i/o ebi address/data bus bit3 a c m p 1_ n ai comparator 1 n egative input pin . 90 56 pc.14 i/o general purpose digital i/o pin. ad2 i/o ebi address/data bus bit2 a c m p 1_ p ai comparator1 p ositive input pin . 91 57 43 pb.15 i/o general purpose digital i/o pin. int1 i external interrupt 1 input pin . t m 0 _ ex t i timer0 external capture input pin. tm0 o timer0 toggle output pin. ad 6 i/o ebi address/data bus bit 6 92 58 44 pf.0 i/o general purpose digital i/o pin. xt1_out o external 4~24 mhz ( high speed ) crystal output pin .
n u m icro ? dec . 30 , 201 4 page 34 of 97 revision 1.0 1 numicro? pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 93 59 45 pf.1 i/o general purpose digital i/o pin. xt1_in i external 4~24 mhz ( high speed ) crystal input pin . 94 60 46 n reset i external reset input: active low , with an internal pull - up . s et this pin low reset chip to initial state. 95 61 v ss p ground pin for digital circuit. 96 62 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 97 pf.2 i/o general purpose digital i/o pin. ps2 _ dat i/o ps2 d ata pin . 98 pf.3 i/o general purpose digital i/o pin. ps2 _ clk i/o ps2 clock pin . 99 63 47 pv ss p pll ground . 100 64 48 pb.8 i/o general purpose digital i/o pin. stadc i adc external trigger input. tm0 i/o timer0 event counter input / toggle output . clko o frequency d ivider clock output pin . note: pin type i = digital input, o = digital output; ai = analog input; p = power pin; ap = analog power
n u m icro ? dec . 30 , 201 4 page 35 of 97 revision 1.0 1 numicro? 4.3.2 numicro ? pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 1 pe.15 i/o general purpose digital i/o pin . 2 pe.14 i/o general purpose digital i/o pin . 3 pe.13 i/o general purpose digital i/o pin . 4 1 pb.14 i/o general purpose digital i/o pin . ad0 i/o ebi address/data bus bit0 int0 i external interrupt 0 input pin . spi3_ss1 i/o 2 nd spi3 slave select pin . 5 2 pb.13 i/o general purpose digital i/o pin . ad1 i/o ebi address/data bus bit1 a c m p 1_ o o comparator 1 output pin . 6 3 1 v bat p power supply by batteries for rtc. 7 4 2 x32 _ o ut o external 32.768 khz (low speed) crystal output pin . 8 5 3 x32 _ i n i external 32.768 khz (low speed) crystal input pin . 9 6 4 pa.11 i/o general purpose digital i/o pin . i2c1 _ scl i/o i 2 c 1 clock pin . can1_rxd i data receiver input pin for can1. nrd o ebi read enable output pin 10 7 5 pa.10 i/o general purpose digital i/o pin . i2c1 _ sda i/o i 2 c 1 data input/output pin . can1_txd o data transmitter output pin for can1. nwr o ebi write enable output pin 11 8 6 pa.9 i/o general purpose digital i/o pin . i2c0 _ scl i/o i 2 c0 clock pin . 12 9 7 pa.8 i/o general purpose digital i/o pin . i2c0 _ sda i/o i 2 c0 data input/output pin . 13 pd.8 i/o general purpose digital i/o pin . spi3_ss 0 i/o 1 st spi3 slave select pin . 14 pd.9 i/o general purpose digital i/o pin . spi3_ clk i/o spi3 serial clock pin . 15 pd.10 i/o general purpose digital i/o pin . spi3_miso 0 i/o 1 st spi3 miso (master in, slave out) pin.
n u m icro ? dec . 30 , 201 4 page 36 of 97 revision 1.0 1 numicro? pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 16 pd.11 i/o general purpose digital i/o pin . spi3_mosi 0 i/o 1 st spi3 mosi (master out, slave in) pin. 17 pd.12 i/o general purpose digital i/o pin . spi3_miso 1 i/o 2 nd spi3 miso (master in, slave out) pin. 18 pd.13 i/o general purpose digital i/o pin . spi3_mosi 1 i/o 2 nd spi3 mosi (master out, slave in) pin. 19 10 8 pb.4 i/o general purpose digital i/o pin . uart1_ rxd i data receiver input pin for uart1 . 20 11 9 pb.5 i/o general purpose digital i/o pin . uart1_ txd o data transmitter output pin for uart1 . 21 12 pb.6 i/o general purpose digital i/o pin . ale o ebi address latch enable output pin uart1_n rts o request to send output pin for uart1 . 22 13 pb.7 i/o general purpose digital i/o pin . ncs o ebi chip select enable output pin uart1_n cts i clear to send input pin for uart1 . 23 14 10 ldo _cap p ldo output pin . 24 15 11 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 25 16 12 v ss p ground pin for digital circuit. 26 pe.8 i/o general purpose digital i/o pin . 27 pe.7 i/o general purpose digital i/o pin . 28 17 13 usb_ v bus usb power supply from usb host or hub . 29 18 14 usb_ v dd 33_cap usb internal power regulator output 3.3v decoupling pin. 30 19 15 usb_ d - usb usb d ifferential s ignal d - . 31 20 16 usb_ d+ usb usb d ifferential s ignal d+ . 32 21 17 pb.0 i/o general purpose digital i/o pin . uart0_ rxd i data receiver input pin for uart0 . 33 22 18 pb.1 i/o general purpose digital i/o pin . uart0_ txd o data transmitter output pin for uart0 . 34 23 pb.2 i/o general purpose digital i/o pin . nwrl o ebi low byte write enable output pin uart0_n rts o request to send output pin for uart0 .
n u m icro ? dec . 30 , 201 4 page 37 of 97 revision 1.0 1 numicro? pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin tm2_ext i timer2 external capture input pin. tm2 o timer2 toggle output pin. acmp0_o o comparator0 output pin. 35 24 pb.3 i/o general purpose digital i/o pin . uart0_n cts i clear to send input pin for uart0 . nwrh o ebi high byte write enable output pin tm3_ext i timer3 external capture input pin. tm3 o timer3 toggle output pin. sc2_cd i smartcard2 card detect pin. 36 25 19 pd.6 i/o general purpose digital i/o pin . can0_rxd i data receiver input pin for can0. 37 26 20 pd.7 i/o general purpose digital i/o pin . can0_txd o data transmitter output pin for can0. 38 27 pd.14 i/o general purpose digital i/o pin . uart2_ rxd i data receiver input pin for uart2 . can1_rxd i data receiver input pin for can1. 39 28 pd.15 i/o general purpose digital i/o pin . uart2_ txd o data transmitter output pin for uart2 . can1_txd o data transmitter output pin for can1. 40 pc.5 i/o general purpose digital i/o pin . spi0_mosi 1 i/o 2 nd spi 0 mosi (master out, slave in) pin. 41 pc.4 i/o general purpose digital i/o pin . spi0_miso 1 i/o 2 nd spi 0 miso (master in, slave out) pin. 42 29 21 pc.3 i/o general purpose digital i/o pin . spi0_mosi 0 i/o 1 st spi 0 mosi (master out, slave in) pin. i2s_do o i 2 s data output. 43 30 22 pc.2 i/o general purpose digital i/o pin . spi0_miso 0 i/o 1 st spi 0 miso (master in, slave out) pin. i2s_di i i 2 s data input. 44 31 23 pc.1 i/o general purpose digital i/o pin . spi0_ clk i/o spi0 s erial clock pin . i2s_bclk i/o i 2 s bit clock pin.
n u m icro ? dec . 30 , 201 4 page 38 of 97 revision 1.0 1 numicro? pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 45 32 24 pc.0 i/o general purpose digital i/o pin . spi0_ss 0 i/o 1 st spi0 slave select pin . i2s_lrc l k i/o i 2 s left right channel clock. 46 pe.6 i/o general purpose digital i/o pin . 47 pe.5 i/o general purpose digital i/o pin . pwm 5 i/o pwm5 output /capture input. tm1_ext i timer1 external capture input pin. tm1 o timer1 toggle output pin. 48 pb.11 i/o general purpose digital i/o pin . tm3 i/o timer3 event counter input / toggle output. pwm 4 i/o pwm4 output /capture input. 49 pb.10 i/o general purpose digital i/o pin . tm2 i/o timer2 event counter input / toggle output. spi0_ss 1 i/o 2 nd spi0 slave select pin . 50 pb.9 i/o general purpose digital i/o pin . tm1 i/o timer1 event counter input / toggle output. spi1_ss 1 i/o 2 nd spi1 slave select pin . 51 pe.4 i/o general purpose digital i/o pin . 52 pe.3 i/o general purpose digital i/o pin . 53 pe.2 i/o general purpose digital i/o pin . 54 pe.1 i/o general purpose digital i/o pin . pwm 7 i/o pwm7 output /capture input. 55 pe.0 i/o general purpose digital i/o pin . pwm 6 i/o pwm6 output /capture input. 56 pc.13 i/o general purpose digital i/o pin . spi1_mosi 1 i/o 2 nd spi 1mosi (master out, slave in) pin. 57 pc.12 i/o general purpose digital i/o pin . spi1_miso 1 i/o 2 nd spi 1 miso (master in, slave out) pin. 58 33 pc.11 i/o general purpose digital i/o pin . spi1_mosi 0 i/o 1 st spi 1 mosi (master out, slave in) pin. 59 34 pc.10 i/o general purpose digital i/o pin . spi1_miso 0 i/o 1 st spi 1 miso (master in, slave out) pin.
n u m icro ? dec . 30 , 201 4 page 39 of 97 revision 1.0 1 numicro? pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 60 35 pc.9 i/o general purpose digital i/o pin . spi1_ clk i/o spi1 s erial clock pin . 61 36 pc.8 i/o general purpose digital i/o pin . mclk o ebi clock output spi1_ss 0 i/o 1 st spi1 slave select pin . 62 37 25 pa.15 i/o general purpose digital i/o pin . pwm3 i/o pwm3 output /capture input. i2s_mclk o i 2 s master clock output pin. sc2_pwr o smartcard2 power pin. 63 38 26 pa.14 i/o general purpose digital i/o pin . pwm2 i/o pwm2 output /capture input. ad15 i/o ebi address/data bus bit15 sc2_rst o smartcard2 reset pin. 64 39 27 pa.13 i/o general purpose digital i/o pin . pwm1 i/o pwm1 output /capture input. ad14 i/o ebi address/data bus bit14 sc2_clk o smartcard2 clock pin. 27 uart5_txd o data transmitter output pin for uart 5. 65 40 28 pa.12 i/o general purpose digital i/o pin . pwm0 i/o pwm0 output /capture input. ad13 i/o ebi address/data bus bit13 sc2_dat o smartcard2 data pin. 28 uart5_rxd i data receiver input pin for uart 5. 66 41 29 ice _ dat i/o serial w ire d ebu g ger d ata pin . 67 42 30 ice_c l k i serial w ire d ebu g ger c lock pin . 68 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 69 v ss p ground pin for digital circuit. 70 43 31 av ss ap ground p in for analog circuit . 71 44 32 pa.0 i/o general purpose digital i/o pin . adc0 ai adc 0 analog input . sc0_pwr o smartcard0 power pin. 72 45 33 pa.1 i/o general purpose digital i/o pin .
n u m icro ? dec . 30 , 201 4 page 40 of 97 revision 1.0 1 numicro? pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin adc1 ai adc 1 analog input . sc0_rst o smartcard0 reset pin. ad12 i/o ebi address/data bus bit12 73 46 34 pa.2 i/o general purpose digital i/o pin . adc2 ai adc2 analog input. sc0_clk o smartcard0 clock pin. uart3_txd o data transmitter output pin for uart 3. ad11 i/o ebi address/data bus bit11 74 47 35 pa.3 i/o general purpose digital i/o pin. adc3 ai adc3 analog input. sc0_dat o smartcard0 data pin. uart3_rxd i data receiver input pin for uart 3. ad10 i/o ebi address/data bus bit10 75 48 36 pa. 4 i/o general purpose digital i/o pin . adc 4 ai adc 4 analog input . ad9 i/o ebi address/data bus bit9 sc1_pwr o smartcard1 power pin. 76 49 37 pa.5 i/o general purpose digital i/o pin. adc 5 ai adc 5 analog input . ad8 i/o ebi address/data bus bit8 sc1_rst o smartcard1 reset pin. 77 50 38 pa.6 i/o general purpose digital i/o pin. adc6 ai adc 6 analog input . ad7 i/o ebi address/data bus bit7 sc1_clk i/o smartcard1 clock pin. uart4_txd o data transmitter output pin for uart 4. 78 pa.7 i/o general purpose digital i/o pin . adc7 ai adc 7 analog input . ad6 i/o ebi address/data bus bit6 sc1_dat o smartcard1 data pin. uart4_rxd i data receiver input pin for uart 4. spi2_ss1 i/o 2 nd spi2 slave select pin .
n u m icro ? dec . 30 , 201 4 page 41 of 97 revision 1.0 1 numicro? pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 79 51 39 v ref ap v oltage reference input for adc. 80 52 40 av dd ap p ower supply for internal analog circuit . 81 pd.0 i/o general purpose digital i/o pin . spi2_ss 0 i/o 1 st spi2 slave select pin . 82 pd.1 i/o general purpose digital i/o pin . spi2_ clk i/o spi2 s erial clock pin . 83 pd.2 i/o general purpose digital i/o pin . spi2_miso 0 i/o 1 st spi 2 miso (master in, slave out) pin. 84 pd.3 i/o general purpose digital i/o pin . spi2_mosi 0 i/o 1 st spi 2 mosi (master out, slave in) pin. 85 pd.4 i/o general purpose digital i/o pin . spi2_miso 1 i/o 2 nd spi 2 miso (master in, slave out) pin. 86 pd.5 i/o general purpose digital i/o pin . spi2_mosi 1 i/o 2nd spi2 mosi (master out, slave in) pin. 87 53 41 pc.7 i/o general purpose digital i/o pin. acmp0_n ai comparator0 negative input pin. ad5 i/o ebi address/data bus bit5 sc1_cd i smartcard1 card detect pin. 88 54 42 pc.6 i/o general purpose digital i/o pin. acmp0_p ai comparator0 positive input pin. sc0_cd i smartcard0 card detect pin. ad4 i/o ebi address/data bus bit4 89 55 pc.15 i/o general purpose digital i/o pin. ad3 i/o ebi address/data bus bit3 acmp1_n ai comparator1 negative input pin . 90 56 pc.14 i/o general purpose digital i/o pin. ad2 i/o ebi address/data bus bit2 acmp1_p ai comparator1 positive input pin. 91 57 43 pb.15 i/o general purpose digital i/o pin . int1 i external interrupt 1 input pin . tm0_ext i timer 0 external capture input pin. tm0 o timer0 toggle output pin. ad 6 i/o ebi address/data bus bit 6
n u m icro ? dec . 30 , 201 4 page 42 of 97 revision 1.0 1 numicro? pin no . pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 92 58 44 pf.0 i/o general purpose digital i/o pin. xt 1 _out o external 4~24 mhz (high speed) crystal output pin . 93 59 45 pf.1 i/o general purpose digital i/o pin . xt 1 _in i external 4~24 mhz (high speed) crystal input pin . 94 60 46 n reset i external reset input : active low , with an internal pull - up. s et this pin low reset chip to initial state . 95 61 v ss p ground pin for digital circuit. 96 62 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 97 pf.2 i/o general purpose digital i/o pin . ps2 _ dat i/o ps / 2 d ata pin . 98 pf.3 i/o general purpose digital i/o pin . ps2 _ clk i/o ps / 2 clock pin . 99 63 47 pv ss p pll ground . 100 64 48 pb.8 i/o general purpose digital i/o pin. stadc i adc external trigger input. tm0 i/o timer0 event counter input / toggle output. clko o frequency divider clock output pin. note: pin type i = digital input, o = digital output; ai = analog input; p = power pin; ap = analog power
n u m icro ? dec . 30 , 201 4 page 43 of 97 revision 1.0 1 numicro? 5 block diagram 5.1 numicro ? figure 5 - 1 numicro ? nuc 23 0 block diagram a r m c o r t e x - m 0 7 2 m h z m e m o r y p d m a a p r o m 1 2 8 / 6 4 / 3 2 k b d a t a f l a s h c o n f i g u r a b l e / 4 k b s r a m 1 6 / 8 k b t i m e r / p w m a n a l o g i n t e r f a c e 3 2 - b i t t i m e r x 4 r t c p w m / c a p t u r e t i m e r x 8 w a t c h d o g t i m e r 1 2 - b i t a d c x 8 p o w e r c o n t r o l c l o c k c o n t r o l l d o p o w e r o n r e s e t l v r b r o w n o u t d e t e c t i o n h i g h s p e e d o s c i l l a t o r 2 2 . 1 1 8 4 m h z h i g h s p e e d c r y s t a l o s c . 4 ~ 2 4 m h z l o w s p e e d o s c i l l a t o r 1 0 k h z p l l c o n n e c t i v i t y u a r t x 3 s p i x 4 i 2 c x 2 p s / 2 x 1 i 2 s x 1 s c ( u a r t ) x 3 i / o p o r t s g e n e r a l p u r p o s e i / o r e s e t p i n e x t e r n a l i n t e r r u p t a n a l o g c o m p a r a t o r x 2 l o w s p e e d c r y s t a l o s c . 3 2 . 7 6 8 k h z l d r o m 8 k b a h b b u s a p b b u s b r i d g e c a n x 2
n u m icro ? dec . 30 , 201 4 page 44 of 97 revision 1.0 1 numicro? 5.2 numicro ? figure 5 - 2 numicro ? nuc 24 0 block diagram a r m c o r t e x - m 0 7 2 m h z m e m o r y a p r o m 1 2 8 / 6 4 / 3 2 k b d a t a f l a s h c o n f i g u r a b l e / 4 k b s r a m 1 6 / 8 k b t i m e r / p w m a n a l o g i n t e r f a c e 3 2 - b i t t i m e r x 4 r t c p w m / c a p t u r e t i m e r x 8 w a t c h d o g t i m e r 1 2 - b i t a d c x 8 p o w e r c o n t r o l c l o c k c o n t r o l l d o p o w e r o n r e s e t l v r b r o w n o u t d e t e c t i o n h i g h s p e e d o s c i l l a t o r 2 2 . 1 1 8 4 m h z h i g h s p e e d c r y s t a l o s c . 4 ~ 2 4 m h z l o w s p e e d o s c i l l a t o r 1 0 k h z p l l c o n n e c t i v i t y u a r t x 3 s p i x 4 i 2 c x 2 p s / 2 x 1 i 2 s x 1 s c ( u a r t ) x 3 i / o p o r t s g e n e r a l p u r p o s e i / o r e s e t p i n e x t e r n a l i n t e r r u p t a n a l o g c o m p a r a t o r x 2 l o w s p e e d c r y s t a l o s c . 3 2 . 7 6 8 k h z u s b l d r o m 8 k b u s b p h y a h b b u s a p b b u s b r i d g e p d m a c a n x 2
n u m icro ? dec . 30 , 201 4 page 45 of 97 revision 1.0 1 numicro? 6 functional descripti on 6.1 arm? cortex? - m0 core the cortex? - m0 processor is a configurable, multistage, 32 - bit risc processor , which has an amba ahb - lite interface and includes an nvic component. it also has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex? - m profile pro cessor. the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an excepti on return. figure 6 - 1 shows the functional controller of processor. figure 6 - 1 functional controller diagram the implemented device provides the following components and features : ? a low gate count processor: - armv6 - m thumb ? instruction set - thumb - 2 technology - armv6 - m compliant 24 - bit systick timer - a 32 - bit hardware multiplier - s ystem interface support ed with little - endian data accesses - a bility to have deterministic, fixed - latency, interrupt handling - load/store - multiples and multicycle - multiplies that can be abandoned and restarted to facilitate rapid inte rrupt handling - c application binary interface compliant exception model. this is the armv6 - m, c application binary interface (c - abi) compliant exception model that enables the use of pure c functions as interrupt handlers - low p ower s leep mode entry using w ait for interrupt (wfi), wait for event (wfe) instructions, or the return from interrupt sleep - on - exit feature c o r t e x t m - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x t m - m 0 p r o c e s s o r c o r t e x t m - m 0 c o m p o n e n t s w a k e u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
n u m icro ? dec . 30 , 201 4 page 46 of 97 revision 1.0 1 numicro? ? nvic: - 32 external interrupt inputs, each with four levels of priority - dedicated non - m askable interrupt (nmi) input - support s for both level - sensit ive and pulse - sensitive interrupt lines - supports wake - up interrupt controller (wic) and , providing u ltra - low p ower s leep mode ? debug support - four hardware breakpoints - two watchpoints - program counter sampling register (pcsr) for non - intrusive code profiling - single step and vector catch capabilities ? bus interfaces: - single 32 - bit amba - 3 ahb - lite system interface that provides simple integration to all system peripherals and memory - single 32 - bit slave port that supports the dap (debug access port)
n u m icro ? dec . 30 , 201 4 page 47 of 97 revision 1.0 1 numicro? 6.2 system manager 6.2.1 overview system management includes the following sections: ? system resets ? system memory map ? system management registers for part number id, chip reset and on - chip controllers reset , multi - functional pin control ? system timer (systick) ? nested vector ed interrupt controller (nvic) ? system control registers 6.2.2 system reset the system reset can be issued by one of the following listed events. for these reset event flags can be read by rstsrc register. ? power - o n reset ? l ow level on the n reset pin ? watchdog time - out reset ? low voltage reset ? brown - out detector reset ? cpu reset ? system reset system reset and power - o n reset all reset the whole chip including all peripherals. the difference between system reset and power - o n reset is external crystal circuit and bs( ispcon [1]) bit. system reset does not reset external crystal circuit and bs( ispcon [1]) bit, but power - o n reset does.
n u m icro ? dec . 30 , 201 4 page 48 of 97 revision 1.0 1 numicro? 6.2.3 system power distribution in this chip, the power distribution is divided into three segments. ? analog power from av dd and av ss provides the power for analog components operation. ? digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 1.8 v power for digital operation and i/o pins. ? usb transceiver power from v bus offers the power for ope rating the usb transceiver. ? battery power from v bat supplies the rtc and external 32.768 khz crystal . the outputs of internal voltage regulators, ldo and v dd33 , require an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level with the digital power (v dd ). e` ! ??? figure 6 - 2 shows the numicro ? nuc 23 0 power distribution , and figure 6 - 3 shows the numicro ? nuc 24 0 power distribution . figure 6 - 2 numicro ? nuc 23 0 power distribution diagram 1 2 - b i t s a r - a d c b r o w n - o u t d e t e c t o r l o w v o l t a g e r e s e t a n a l o g c o m p a r a t o r t e m p e r a t u r e s e n e o r f l a s h d i g i t a l l o g i c i n t e r n a l 2 2 . 1 1 8 4 m h z & 1 0 k h z o s c i l l a t o r a v d d a v s s l d o _ c a p 1 u f g p i o n u c 2 3 0 p o w e r d i s t r i b u t i o n l d o p l l p o r 5 0 p o r 1 8 e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l v d d v s s i o c e l l x 3 2 _ u t o x 3 2 _ i n p v s s v b a t r t c u l d o 1 . 8 v 1 . 8 v
n u m icro ? dec . 30 , 201 4 page 49 of 97 revision 1.0 1 numicro? figure 6 - 3 numicro ? nuc 24 0 power distribution diagram l d o u s b 1 . 1 t r a n c e i v e r 5 v t o 3 . 3 v l d o p l l 1 2 - b i t s a r - a d c b r o w n - o u t d e t e c t o r p o r 5 0 p o r 1 8 l o w v o l t a g e r e s e t e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l a n a l o g c o m p a r a t o r t e m p e r a t u r e s e n e o r f l a s h d i g i t a l l o g i c 3 . 3 v 1 . 8 v i n t e r n a l 2 2 . 1 1 8 4 m h z & 1 0 k h z o s c i l l a t o r a v d d a v s s v d d v s s u s b _ v b u s u s b _ v d d 3 3 _ c a p u s b _ d + u s b _ d - l d o _ c a p 1 u f 1 u f i o c e l l g p i o x 3 2 _ o u t x 3 2 _ i n p v s s n u c 2 4 0 p o w e r d i s t r i b u t i o n v b a t r t c u l d o 1 . 8 v
n u m icro ? dec . 30 , 201 4 page 50 of 97 revision 1.0 1 numicro? 6.2.4 system memory map the numicro ? nuc230/240 s eries provides 4g - byte addressing space. the memory locations assigned to each on - chip controllers are shown in the following table. the detailed register definition, memory space, and programming detailed will be described in the following sections for each on - chip peripheral. the numicro ? nuc230/240 s eries only supports little - end ian data format. address space token controllers flash and sram memory space 0x0000_0000 C 0x0001_ffff flash_ba flash memory space (128 kb) 0x2000_0000 C 0x2000_3fff sram_ba sram memory space (16 kb) ahb controllers space (0x5000_0000 C 0x501f_ffff) 0x5000_0000 C 0x5000_01ff gcr_ba system global control registers 0x5000_0200 C 0x5000_02ff clk_ba clock control registers 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gpio_ba gpio control registers 0x5000_8000 C 0x5000_bfff pdma_ba peripheral dma control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers 0x5001_0000 C 0x5001_03ff ebi_ba external bus interface control registers apb1 controllers space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 C 0x4000_7fff wdt_ba watchdog timer control registers 0x4000_8000 C 0x4000_bfff rtc_ba real time clock (rtc) control register 0x4001_0000 C 0x4001_3fff tmr01_ba timer0/timer1 control registers 0x4002_0000 C 0x4002_3fff i2c0_ba i 2 c0 interface control registers 0x4003_0000 C 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 C 0x4003_7fff spi1_ba spi1 with master/slave function control registers 0x4004_0000 C 0x4004_3fff pwma_ba pwm0/1/2/3 control registers 0x4005_0000 C 0x4005_3fff uart0_ba uart0 control registers 0x4006_0000 C 0x4006_3fff usbd_ba usb 2.0 fs device controller registers 0x400d_0000 C 0x400d_3fff acmp_ba analog comparator control registers 0x400e_0000 C 0x400e_ffff adc_ba analog - digital - converter (adc) control registers apb2 controllers space (0x4010_0000 ~ 0x401f_ffff) 0x4010_0000 C 0x4010_3fff ps2_ba ps/2 interface control registers 0x4011_0000 C 0x4011_3fff tmr23_ba timer2/timer3 control registers 0x4012_0000 C 0x4012_3fff i2c1_ba i 2 c1 interface control registers 0x4013_0000 C 0x4013_3fff spi2_ba spi2 with master/slave function control registers 0x4013_4000 C 0x4013_7fff spi3_ba spi3 with master/slave function control registers
n u m icro ? dec . 30 , 201 4 page 51 of 97 revision 1.0 1 numicro? 0x4014_0000 C 0x4014_3fff pwmb_ba pwm4/5/6/7 control registers 0x4015_0000 C 0x4015_3fff uart1_ba uart1 control registers 0x4015_4000 C 0x4015_7fff uart2_ba uart2 control registers 0x4018_0000 C 0x4018_3fff can0_ba can0 bus control registers 0x4018_4000 C 0x4018_7fff can1_ba can1 bus control registers 0x4019_0000 C 0x4019_3fff sc0_ba sc0 control registers 0x4019_4000 C 0x4019_7fff sc1_ba sc1 control registers 0x4019_8000 C 0x4019_bfff sc2_ba sc2 control registers 0x401a_0000 C 0x401a_3fff i2s_ba i 2 s interface control registers system controllers space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 C 0xe000_e0ff scs_ba system timer control registers 0xe000_e100 C 0xe000_ecff scs_ba external interrupt controller control registers 0xe000_ed00 C 0xe000_ed8f scs_ba system control registers table 6 - 1 address space assignments for on - chip controllers
n u m icro ? dec . 30 , 201 4 page 52 of 97 revision 1.0 1 numicro? 6.2.5 system timer (systick) the cortex? - m0 includes an integrated system timer, systick , which provides a simple, 24 - bit clear - on - wri te, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count down from the value in the systick curre nt value register (syst_cvr) to 0 , and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock cycle, then decrement on subsequent clocks. when the counter transitions to 0 , the countflag status bit is set. the countfla g bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to 0 before enabling the feature. this ensures the timer will count from the syst_rvr value rather than an arbitrary value when it is enabled. if the syst_rvr is 0 , the timer will be maintained with a current value of 0 after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the arm ? cortex? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
n u m icro ? dec . 30 , 201 4 page 53 of 97 revision 1.0 1 numicro? 6.2.6 nested vectored interrupt controller (nvic) the cortex? - m0 provides an interrupt controller as an integral part of the exception mode, named as nested vectored interrupt controller (nvic) , which is closely coupled to the processor kernel and provides following features: ? nested and vectored interrupt support ? automatic processor state saving and restoration ? reduced and deterministic interrupt latency the nvic prio ritizes and handles all supported exceptions. all exceptions are handled in handler mode. this nvic architecture supports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configu red to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running ones priority. if the priority of the new interrupt is higher than the current one, the new interrupt handler will o verride the current handler. when a n interrupt is accepted, the starting address of the interrupt service routine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address o f the correlated isr by software. while the starting address is fetched, nvic will also automatically save processor state including the registers pc, psr, lr, r0~r3, r12 to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports tail chaining which handles back - to - back interrupts efficiently without the overhead of states saving and restor ation and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic also supports late arrival which improves the efficiency of concurrent isrs. when a higher priority interrupt request occurs before the current isr sta rts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the real - time capability. for more detailed information, please refer to the arm ? cortex? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
n u m icro ? dec . 30 , 201 4 page 54 of 97 revision 1.0 1 numicro? 6.2.6.1 exception model and system interrupt map the following table lists the exception model supported by numicro ? nuc230/240 s eries . software can set four levels of priority on some of these exceptions as well as on all interrupts. the highest user - configurable priority is denoted as 0 and the lowest priority is denoted as 3. the default priority of all the user - configurable interrupts is 0. note that priority 0 is treated as the fourth priority on the system, after three system exceptions reset, nmi and hard fault. exception name vector number priority reset 1 - 3 nmi 2 - 2 hard fault 3 - 1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 6 - 2 exception model vector number interrupt number ( bit in interrupt registers ) interrupt name source module interrupt description 1 ~ 15 - - - system exceptions 16 0 bod_ int brown - out brown - out low voltage detected interrupt 17 1 wdt_int wdt watchdog timer interrupt 18 2 eint0 gpio external signal interrupt from pb.14 pin 19 3 eint1 gpio external signal interrupt from pb.15 pin 20 4 gpab_int gpio external signal interrupt from pa[15:0]/pb[13:0] 21 5 gpcdef_int gpio external interrupt from pc[15:0]/pd[15:0]/pe[15:0]/pf[3:0] 22 6 pwma_int pwm0~3 pwm0, pwm1, pwm2 and pwm3 interrupt 23 7 pwmb_int pwm4~7 pwm4, pwm5, pwm6 and pwm7 interrupt 24 8 tmr0_int tmr0 timer 0 interrupt 25 9 tmr1_int tmr1 timer 1 interrupt 26 10 tmr2_int tmr2 timer 2 interrupt 27 11 tmr3_int tmr3 timer 3 interrupt 28 12 uart02_int uart0/2 uart0 and uart2 interrupt 29 13 uart1_int uart1 uart1 interrupt 30 14 spi0_int spi0 spi0 interrupt
n u m icro ? dec . 30 , 201 4 page 55 of 97 revision 1.0 1 numicro? 31 15 spi1_int spi1 spi1 interrupt 32 16 spi2_int spi2 spi2 interrupt 33 17 spi3_int spi3 spi3 interrupt 34 18 i2c0_int i 2 c0 i 2 c0 interrupt 35 19 i2c1_int i 2 c1 i 2 c1 interrupt 36 20 - - reserved 37 21 - - reserved 38 22 sc012_int sc0/1/2 sc0, sc1 and sc2 interrupt 39 23 usb_int usbd usb 2.0 fs device interrupt 40 24 ps2_int ps/2 ps/2 interrupt 41 25 acmp_int acmp analog comparator interrupt 42 26 pdma_int pdma pdma interrupt 43 27 i2s_int i 2 s i 2 s interrupt 44 28 pwrwu_int clkc clock controller interrupt for chip wake - up from power - down state 45 29 adc_int adc adc interrupt 46 30 irc_int irc irc trim interrupt 47 31 rtc_int rtc real t ime c lock interrupt table 6 - 3 system interrupt map
n u m icro ? dec . 30 , 201 4 page 56 of 97 revision 1.0 1 numicro? 6.2.6.2 vector table when an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. for armv6 - m, the vector table base address is fixed at 0x00000000. the vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. the vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. vector table word offset description 0 sp_main C the main stack pointer vector number exception entry pointer using that vector number table 6 - 4 vector table format 6.2.6.3 operation description nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set - enable or interrupt clear - enable register bit - field. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current enabled state of the corresponding interrupts. when an interrupt is disabled, interrupt assertion will cause the interrupt to become pending, however, the interrupt will not activate. if an interrupt is active when it is disabled, it remains in its active state until cleared by reset or an exception return. clearing the enable bit prevents new activations of the associated interrupt. nvic interrupts can be pended/un - pended using a complem entary pair of registers to those used to enable/disable the interrupts, named the set - pending register and clear - pending register respectively. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current pend ed state of the corresponding interrupts. the clear - pending register has no effect on the execution status of an active interrupt. nvic interrupts are prioritized by updating an 8 - bit field within a 32 - bit register (each register supporting four interrupts ). the general registers associated with the nvic are all accessible from a block of memory in the system control space and will be described in next section. 6.2.7 system control the cortex? - m0 status and operating mode control are managed by system control registers. including cpuid, cortex? - m0 interrupt priority and cortex? - m0 power management can be controlled through these system control register s . for more detailed information, please refer to the arm ? cortex? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
n u m icro ? dec . 30 , 201 4 page 57 of 97 revision 1.0 1 numicro? 6.3 clock controller 6.3.1 overview the clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also implements the power control function with the individ ually clock on/off control, clock source selection and clock divider. the chip enters power - down mode when cortex? - m0 core executes the wfi instruction only if the pwr_down_en (pwrcon[7]) bit and pd_wait_cpu (pwrcon[8]) bit are both set to 1 . after that, chip enter s power - down mode and wait for wake - up interrupt source triggered to leave power - down mode. in the power - down mode, the clock controller turns off the 4~24 mhz external high speed crystal oscillator and 22.1184 mhz internal high speed rc oscillat or to reduce the overall system power consumption. the following figures show the clock generator and the overview of the clock source control. the clock generator consists of 5 clock sources as listed below: ? 32.768 khz external low speed crystal oscillat or (lxt) ? 4~24 mhz external high speed crystal oscillator (hxt) ? p rogrammable pll output clock frequency (pll source can be selected from external 4~24 mhz external high speed crystal oscillator (hxt) or 22.1184 mhz internal high speed rc oscillator (hirc)) (pll fout ) ? 22.1184 mhz i nternal high speed rc oscillator (hirc) ? 10 khz internal low speed rc oscillator (lirc)
n u m icro ? dec . 30 , 201 4 page 58 of 97 revision 1.0 1 numicro? figure 6 - 4 clock g enerator b lock d iagram x t 1 _ i n 4 ~ 2 4 m h z h x t x t l 1 2 m _ e n ( p w r c o n [ 0 ] ) x t 1 _ o u t 2 2 . 1 1 8 4 m h z h i r c o s c 2 2 m _ e n ( p w r c o n [ 2 ] ) 0 1 p l l p l l _ s r c ( p l l c o n [ 1 9 ] ) p l l f o u t 1 0 k h z l i r c o s c 1 0 k _ e n ( p w r c o n [ 3 ] ) h x t h i r c l i r c l e g e n d : l x t = 3 2 . 7 6 8 k h z e x t e r n a l l o w s p e e d c r y s t a l o s c i l l a t o r h x t = 4 ~ 2 4 m h z e x t e r n a l h i g h s p e e d c r y s t a l o s c i l l a t o r h i r c = 2 2 . 1 1 8 4 m h z i n t e r n a l h i g h s p e e d r c o s c i l l a t o r l i r c = 1 0 k h z i n t e r n a l l o w s p e e d r c o s c i l l a t o r x 3 2 _ i n 3 2 . 7 6 8 k h z l x t x t l 3 2 k _ e n ( p w r c o n [ 1 ] ) x 3 2 _ o u t l x t
n u m icro ? dec . 30 , 201 4 page 59 of 97 revision 1.0 1 numicro? figure 6 - 5 clock g enerator g lobal v iew d iagram 1 0 p l l c o n [ 1 9 ] 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z p l l f o u t 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z h c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2 c l k s e l 0 [ 5 : 3 ] 1 0 s y s t i c k t m r 0 a d c u a r t 0 - 2 p d m a a c m p i 2 c 0 ~ 1 i 2 s r t c p w m 0 - 1 w d t p w m 2 - 3 p w m 4 - 5 p w m 6 - 7 t m r 3 t m r 2 t m r 1 c p u f m c 3 2 . 7 6 8 k h z 1 0 k h z 0 1 1 0 1 0 0 0 1 0 0 0 h c l k 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 0 k h z 2 2 . 1 1 8 4 m h z 0 0 0 c l k s e l 0 [ 2 : 0 ] s y s t _ c s r [ 2 ] c p u c l k 1 / ( h c l k _ n + 1 ) p c l k c p u c l k h c l k 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z h c l k c l k s e l 1 [ 3 : 2 ] e x t e r n a l t r i g g e r c l k s e l 1 [ 2 2 : 2 0 ] c l k s e l 1 [ 1 8 : 1 6 ] c l k s e l 1 [ 1 4 : 1 2 ] c l k s e l 1 [ 1 0 : 8 ] 1 1 1 0 0 1 0 0 h c l k p l l f o u t 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 0 1 1 0 1 0 0 0 1 0 0 0 h c l k 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z w w d t 1 0 k h z 1 / ( a d c _ n + 1 ) c l k s e l 2 [ 1 : 0 ] 1 1 1 0 c l k s e l 1 [ 1 : 0 ] h c l k 1 / 2 0 4 8 1 / ( u a r t _ n + 1 ) 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z 0 1 3 2 . 7 6 8 k h z 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z c l k s e l 1 [ 2 5 : 2 4 ] 2 2 . 1 1 8 4 m h z 1 0 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z h c l k c l k s e l 3 [ 5 : 4 ] 2 2 . 1 1 8 4 m h z 1 0 s c 2 1 / ( s c 2 _ n + 1 ) c l k s e l 3 [ 3 : 2 ] c l k s e l 3 [ 1 : 0 ] s c 1 1 / ( s c 1 _ n + 1 ) s c 0 1 / ( s c 0 _ n + 1 ) 1 0 k h z 2 2 . 1 1 8 4 m h z 1 0 1 1 1 1 1 0 s p i 0 - 3 c l k _ s e l 1 [ 7 : 4 ] h c l k u s b 1 / ( u s b _ n + 1 ) p l l f o u t 1 1 1 0 0 1 0 0 h c l k 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z c l k s e l 2 [ 3 : 2 ] f d i v b o d 1 0 k h z 1 1 1 0 c l k s e l 2 [ 1 7 : 1 6 ] 1 0 k h z c l k s e l 2 [ 1 1 : 4 ] c l k s e l 1 [ 3 1 : 2 8 ] 1 0 k h z 1 1 1 p s 2 2 2 . 1 1 8 4 m h z c a n 0 ~ 1 p l l f o u t 1 0 c l k s e l 2 [ 1 8 ] 1 0 k h z
n u m icro ? dec . 30 , 201 4 page 60 of 97 revision 1.0 1 numicro? 6.3.2 system clock and systick clock the system clock has 5 clock sources which were generated from clock generator block. the clock source switch depends on the register hclk_s (clksel0[2:0]). the block diagram is show n in figure 6 - 6 . figure 6 - 6 system clock block diagram the clock source of systick in cortex? - m0 core can use cpu clock or exter nal clock (syst_csr[2]). if using external clock, the systick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of the register stclk_s (clksel0[5:3]). the block diagram is show n in figure 6 - 7 . figure 6 - 7 systick clock control block diagram 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 0 k h z h c l k _ s ( c l k s e l 0 [ 2 : 0 ] ) 2 2 . 1 1 8 4 m h z 0 0 0 1 / ( h c l k _ n + 1 ) h c l k _ n ( c l k d i v [ 3 : 0 ] ) c p u i n p o w e r d o w n m o d e c p u a h b a p b c p u c l k h c l k p c l k 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z h c l k s t c l k _ s ( c l k s e l 0 [ 5 : 3 ] ) s t c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2
n u m icro ? dec . 30 , 201 4 page 61 of 97 revision 1.0 1 numicro? 6.3.3 power - down mode clock when chip enters power - down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. some clock sources and peripherals clock s are still active in power - down mode. the clocks still kep t active are list ed below: ? clock generator - 10 khz i nternal low speed rc oscillator clock - 32.768 khz e xternal low speed crystal oscillator clock ? rtc/wdt/timer/pwm peripherals clock ( w hen 32.768 khz external low speed crystal oscillator or 10 khz inte r tnal low speed rc oscillator is adopted as clock source)
n u m icro ? dec . 30 , 201 4 page 62 of 97 revision 1.0 1 numicro? 6.3.4 frequency divide r output this device is equipped with a power - of - 2 frequency divider which is composed by16 chained divide - by - 2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to clko function pin. therefore ther e are 16 options of power - of - 2 divided clocks with the frequency from f in /2 1 to f in /2 16 where fin is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4 - bit value in fsel (frqdiv[3:0]). when writ ing 1 to divider_en (frqdiv[4]), the chained counter starts to count. when writ ing 0 to divider_en (frqdiv[4]), the chained counter continuously runs till divid ed clock reaches low state and stay in low state. i f divider1(frqdiv[5]) is set to 1, the frequency divider clock (frqdiv_clk) will bypass power - of - 2 frequency divider. the frequency divider clock will be output to c l ko pin directly. figure 6 - 8 clock source of frequency divider figure 6 - 9 frequency divider block diagram 1 1 1 0 0 1 0 0 h c l k 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z f r q d i v _ s ( c l k s e l 2 [ 3 : 2 ] ) f d i v _ e n ( a p b c l k [ 6 ] ) f r q d i v _ c l k 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 : : 1 6 t o 1 m u x 1 / 2 1 / 2 2 1 / 2 3 1 / 2 1 5 1 / 2 1 6 . . . f s e l ( f r q d i v [ 3 : 0 ] ) c l k o f r q d i v _ c l k 1 6 c h a i n e d d i v i d e - b y - 2 c o u n t e r d i v i d e r _ e n ( f r q d i v [ 4 ] ) e n a b l e d i v i d e - b y - 2 c o u n t e r 0 1 d i v i d e r 1 ( f r q d i v [ 5 ] )
n u m icro ? dec . 30 , 201 4 page 63 of 97 revision 1.0 1 numicro? 6.4 f lash m emory c ontroller (fmc) 6.4.1 overview the numicro ? nuc230/240 s eries has 128/64/32k bytes on - chip embedded flash for application program memory (aprom) that can be updated through isp procedure. the i n - system - programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip is power ed on, cortex? - m0 cpu fetches code from aprom or ldrom decided by boot select (cbs) in config0 . by the way, the numicro ? nuc230/240 s eries als o provides additional data flash for user to store some application dependent data. for 128k bytes aprom device, the data flash is shared with original 128k program memory and its start address is configurable in config1 . for 64k/32k bytes aprom device, th e data flash is fixed at 4 k b . 6.4.2 features ? run s up to 50 mhz with zero wait cycle for continuous address read access and runs up to 72mhz with one wait cycle for continuous address read. ? all embedded flash memory supports 512 bytes page erase ? 128/64/32 kb application program memory (aprom) ? 8 kb i n - s ystem - p rogramming (isp) loader program memory (ldrom) ? 4kb data flash for 64/32 kb aprom device ? configurable data flash size for 128kb aprom device ? configurable or fixed 4 kb data flash with 512 bytes page erase unit ? support s in - application - programming (iap) to switch code between aprom and ldrom without reset ? in - system - program ming (isp) to update on - chip flash
n u m icro ? dec . 30 , 201 4 page 64 of 97 revision 1.0 1 numicro? 6.5 e xternal bus interface (ebi) 6.5.1 overview the numicro ? nuc1 00 series lqfp - 64 an d lqfp - 100 package equips an external bus interface (ebi) for access external device. to save the connections between external device and this chip, ebi support s address bus and data bus multiplex mode. and, address latch enable (ale) signal is used to dif ferentiate the address and data cycle. 6.5.2 features external bus interface has the following functions: ? supports e xternal devices with max. 64 k b size (8 - bit data width)/128 k b (16 - bit data width) ? supports v ariable external bus base clock (mclk) which based on hclk ? supports 8 - bit or 16 - bit data width ? supports v ariable data access time (tacc), address latch enable time (tale) and address hold time (tahd) ? supports a ddress bus and data bus multiplex mode to save the address pins ? supports c onfigurable idle cycle for different access condition: write command finish (w2x), read - to - read (r2r)
n u m icro ? dec . 30 , 201 4 page 65 of 97 revision 1.0 1 numicro? 6.6 general purpose i/o (gpio) 6.6.1 overview the numicro ? nuc230/240 series has up to 84 general purpose i/o pins to be shared with other function pins depend ing on the chip configurat ion. these 84 pins are arranged in 6 ports named as gpioa, gpiob, gpioc, gpiod, gpioe and gpiof. the gpioa/b/c/d/e port has the maximum of 16 pins and gpiof port has the maximum of 4 pins. each o f the 84 pins is independent and has the corresponding regist er bits to control the pin mode function and data. the i/o type of each of i/o pins can be configured by software individually as input, output, open - drain or q uasi - bidirectional mode. after reset, the i/o mode of all pins are depending on config0[10] setting . in quasi - bidirectional mode, i/o pin has a very weak individual pull - up resistor which is about 110~300 k ? for v dd is from 5.0 v to 2.5 v. 6.6.2 features ? four i/o modes: - quasi - bidirection al - push - pull output - open - drain output - input only with high impende nce ? ttl/schmitt trigger input selectable by gpx_type[15:0] in gpx_mfp[31:16] ? i/o pin configured as interrupt source with edge/level setting ? configurable default i/o mode of all pins after reset by config0[10] setting - if config[10] is 0, all gpio pins in in put tri - state mode after chip reset - if config[10] is 1, all gpio pins in quasi - bidirectional mode after chip reset ? i/o pin internal pull - up resistor enabled only in quasi - bidirectional i/o mode ? enabling the pin interrupt function will also enable the pin w ake - up function . 6.7 p dma controller ( p dma) 6.7.1 overview the numicro ? nuc230/240 series dma contains nine - channel peripheral direct memory access (pdma) controller and a cyclic redundancy check (crc) generator. the pdma that transfers data to and from memory or transfer data to and from apb devices. for pdma channel (pdma ch0~ch8), there is one - word buffer as transfer buffer between the peripherals apb devices and memory. software can stop the pdma operation by disable pdma pdmacen (pdma_csrx[0]). the cpu can rec ognize the completion of a pdma operation by software polling or when it receives an internal pdma interrupt. the pdma controller can increase source or destination address or fixed them as well. the dma controller contains a cyclic redundancy check (crc) generator that can perform crc calculation with programmable polynomial settings. the crc engine supports cpu pio mode and dma transfer mode.
n u m icro ? dec . 30 , 201 4 page 66 of 97 revision 1.0 1 numicro? 6.7.2 features ? supp orts nine pdma channels and one crc channel. each pdma channel can support a unidirectional trans fer ? amba ahb master/slave interface compatible, for data transfer and register read/write ? hardware round robin priority scheme. dma channel 0 has the highest priority and channel 8 has the lowest priority ? pdma oper ation - peripheral - to - memory, memory - to - peri pheral, and memory - to - memory transfer - supports word/half - word/byte transfer data width from/to peripheral - supports ad dress direction: increment, fixed. ? cyclic redundancy check (crc) - supports four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 ? crc - ccitt: x 16 + x 12 + x 5 + 1 ? crc - 8: x 8 + x 2 + x + 1 ? crc - 16: x 16 + x 15 + x 2 + 1 ? crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 - supports p ro grammable crc seed value. - supports programmable order reverse setting for input data and crc checksum. - supports programmable 1s complement setting for input data and crc checksum. - supports cpu pio mode or dma transfer mode. - supports the follows write data length in cpu pio mode ? 8 - bit write mode (byte): 1 - ahb clock cycle operation. ? 16 - bit write mode (half - word): 2 - ahb clock cycle operation. ? 32 - bit write mode (word): 4 - ahb clock cycle operation. - support s byte alignment transfer data length and word alignment transfer source address in crc dma mode. 6.8 timer controller (t i m e r) 6.8.1 overview the timer controller includes four 32 - bit timers, timer0 ~ timer3, allow ing user to easily implement a timer control for applications. the timer can perform functions , such as frequency measurement, delay timing, clock generation, and event counti ng by external input pins, and interval measurement by external capture pins .
n u m icro ? dec . 30 , 201 4 page 67 of 97 revision 1.0 1 numicro? 6.8.2 features ? four sets of 32 - bit timers with 24 - bit up counter and one 8 - bit prescale counter ? independent clock source for each timer ? provides four timer counting modes: one - shot, p eriodic, toggle and continuous counting ? time - out period = (period of timer clock input) * (8 - bit prescale counter + 1) * (24 - bit tcmp) ? maximum counting cycle time = (1 / t mhz) * (2 8 ) * (2 24 ), t is the period of timer clock ? 24 - bit up count er value is readable through tdr (timer data register) ? support s event counting function to count the event from external counter pin (tm0~tm3) ? support s external pin capture (tm0_ext~tm3_ext) for interval measurement ? support s external pin capture (tm0_ext~tm3 _ext) for reset 24 - bit up counter ? supports chip wake - up from idle/power - down mode if a timer interrupt signal is generated
n u m icro ? dec . 30 , 201 4 page 68 of 97 revision 1.0 1 numicro? 6.9 pwm generator and capture timer (pwm) 6.9.1 overview the numicro ? nuc230/240 series has 2 sets of pwm group support ing a total of 4 sets of pwm g enerators that can be configured as 8 independent pwm outputs, pwm0~pwm7, or as 4 complementary pwm pairs, (pwm0, pwm1), (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) with 4 programmable d ead - zone generators. each pwm g enerator has one 8 - bit prescal er, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16 - bit pwm counters for pwm period control, two 16 - bit comparators for pwm duty control and one d ead - zone generator. the 4 sets of pwm g enerators provide eight independent pwm interrupt flags set by hardware when the corresponding pwm period down counter reaches 0 . each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured as one - shot mode to produce only one pwm cycle signal or auto - reload mode to output pwm waveform continuously. when dzen01 ( pcr [4]) is set, pwm0 and pwm1 perform complementary pwm paired function; the paired pwm period, duty and d ead - time are determined by pwm0 timer and dead - zone generator 0. similarly, the complementary pwm pairs of (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) are controlled by pwm2, pwm4 and pwm6 timers and dead - zone generator 2, 4 and 6, respectively. refer to e` ! ??? and e` ! ??? for the architecture of p wm timers. to prevent pwm driving output pin with unsteady waveform, the 16 - bit period down counter and 16 - bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers the updated value will be load into t he 16 - bit down counter/ comparator at the time down counter reaching 0 . the double buffering feature avoids glitch at pwm outputs. when the 16 - bit period down counter reaches 0 , the interrupt request is generated. if pwm - timer is set as auto - reload mode, w hen the down counter reaches 0 , it is reloaded with pwm counter register (cnrx) automatically then start decreasing, repeatedly. if the pwm - timer is set as one - shot mode, the down counter will stop and generate one interrupt request when it reaches 0 . the value of pwm counter comparator is used for pulse high width modulation. the counter control logic changes the output to high level when down - counter value matches the value of compare register. the alternate feature of the pwm - timer is digital input captu re function. if capture function is enabled the pwm output pin is switched as capture input mode. the capture0 and pwm0 share one timer which is included in pwm0 and the capture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm - timer b efore enable capture feature. after capture feature is enabled, the capture always latched pwm - counter to capture rising latch register (crlr) when input channel has a rising transition and latched pwm - counter to capture falling latch register (cflr) when input channel has a falling transition. capture channel 0 interrupt is programmable by setting crl_ie0 ( ccr0[1] ) (rising latch interrupt enable) and cfl_ie0 ( ccr0[2] ) (falling latch interrupt enable) to decide the condition of interrupt occur. capture chan nel 1 has the same feature by setting crl_ie1 ( ccr0[17] ) and cfl_ie1 ( ccr0[18] ) . and capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in ccr2. for each group, whenever capture issues interrupt 0/1 /2/3, the pwm counter 0/1/2/3 will be reload at this moment. the maximum captured frequency that pwm can capture is confined by the capture interrupt latency. when capture interrupt occurred, software will do at least three steps, including : read piir to g et interrupt source and read crlrx/cflrx(x=0~3) to get capture value and finally write 1 to clear piir to 0 . if interrupt latency will take time t0 to finish, the capture signal mustnt transition during this interval (t0). in this case, the maximum captur e frequency will be 1/t0. for
n u m icro ? dec . 30 , 201 4 page 69 of 97 revision 1.0 1 numicro? example: hclk = 50 mhz, pwm_clk = 25 mhz, interrupt latency is 900 ns so the maximum capture frequency will be 1/900ns 1000 khz 6.9.2 features 6.9.2.1 pwm f unction: ? up to 2 pwm group s (pwma/pwmb) to support 8 pwm channels or 4 complementary pwm paired channels ? each pwm group has two pwm generators with e ach pwm generator support ing one 8 - bit prescaler, two clock divider, two pwm - timers, one d ead - zone generator and two pwm outputs. ? up to 16 - bit resolution ? pwm interrupt request sy nchronized with pwm period ? one - shot or auto - reload mode ? edge - aligned type or c enter - aligned type option ? pwm trigger adc start - to - conversion 6.9.2.2 capture function: ? timing control logic shared with pwm generators ? support s 8 capture input channels shared with 8 pwm output channels ? each channel supports one rising latch register (crlr), one falling latch register (cflr) and capture interrupt flag (capifx)
n u m icro ? dec . 30 , 201 4 page 70 of 97 revision 1.0 1 numicro? 6.10 watchdog timer (wdt) 6.10.1 overview the purpose of watchdog timer is to pe rform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports the function to wake - up system from idle/power - down mode. 6.10.2 features ? 18 - bit free running up counter for watchdog t imer time - out interval . ? selectable time - out interval (2 4 ~ 2 18 ) wdt_clk cycle and the time - out interval period is 104 ms ~ 26.3168 s if wdt_clk = 10 khz. ? system kept in reset state for a period of (1 / wdt_clk) * 63 ? supports watchdog t imer reset delay period - s electable it includes (1026 130 18 or 3) * wdt_clk reset delay period . ? supports to force watchdog t imer enabled after chip powered on or reset while cwdten (c onfig 0[31] w atchdog e nable) bit is set to 0. ? supports watchdog timer tim e - out wake - up function only if wdt clock source is selected as 10 khz
n u m icro ? dec . 30 , 201 4 page 71 of 97 revision 1.0 1 numicro? 6.11 window watchdog timer (wwdt) 6.11.1 overview the window watchdog timer is used is to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.11.2 features ? 6 - bit dow n counter value (wwdtval[5:0]) and 6 - bit compare window value (wwdtcr[21:16]) to make the wwd t time - out window period flexible ? s upports 4 - bit value to programmable maximum 11 - bit prescale counter period of wwdt counter 6.12 real time clock (rtc) 6.12.1 overview the real time clock (rtc) controller provides the real time and calendar message. the rtc offers p rogrammable time tick and alarm match interrupts. the data format of time and calendar messages are expressed in bcd format. a digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy. the rtc control ler also offers 80 bytes spare registers to store users important information. 6.12.2 features ? supports real time counter in time loading register (tlr) (hour , minute , second) and calendar counter in calendar loading register (clr) (year , month , day) for rtc time and calendar check ? su pports alarm time (hour , minute , second ) and calendar (year , month , day) settings in time alarm register (tar) and calendar alarm register (car) register ? selectable 12 - hour or 24 - hour time scale in time scale selection register (t ssr) register ? supports leap y ear indication in leap year indicator register (lir) register ? supports day of the w eek counter in day of the week register (dwr) register ? frequency of rtc clock source compensate by rtc frequency compensation register (fcr) reg ister ? all time and calendar message expressed in bcd format ? support s periodic rtc t ime t ick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? support s rtc time tick and alarm match interrupt ? support s chip wake - up from idle or power - down mode while a rtc interrupt signal is generated ? s upports 80 bytes spare registers
n u m icro ? dec . 30 , 201 4 page 72 of 97 revision 1.0 1 numicro? 6.13 uart interface controller (uart) 6.13.1 overview the numicro nuc230/240 series provides up to three channels of universal asynchronous receiver/transmitters (uart). uart0 supports high speed uart and uart1~2 perform normal speed uart. besides, only uart0 and uart1 support the flow control function. the uart controller perform s a serial - to - parallel conversion on data received from the peripheral, and a parallel - to - serial conversion on data transmitted from the cpu. the uart controller also supports irda sir function, lin master/slave function and rs - 485 function mode. each uart controller channel supports seven types of interrupts. 6.13.2 features ? full duplex, asynchronous communications ? separate s receive / transmit 64/16/16 bytes (uart0/uart1/uart2) entry fifo for data payloads ? support s hardware auto flow control/flow control functio n (cts, rts) and programmable rts flow control trigger level (uart0 and uart1 support) ? programmable receiver buffer trigger level ? support s programmable baud - rate generator for each channel individually ? support s cts wake - up function (uart0 and uart1 support ) ? support s 7 - bit receiver buffer time - out detection function ? uart0/uart1 can through dma channels to receive/transmit data ? programmable transmitting data delay time between the last stop and the next start bit by setting ua_tor [dly] register ? support s brea k error, frame error, parity error and receive / transmit buffer overflow detect function ? fully programmable serial - interface characteristics - progra mmable data bit length , 5 - , 6 - , 7 - , 8 - bit character - progra mmable parity bit, even, odd, no parity or stick p arity bit generation and detection - programmable stop bit length , 1, 1.5, or 2 stop bit generation ? irda sir function mode - support s 3 - /16 - bit duration for normal mode ? lin function mode - support s lin master/slave mode - suppo rt s programmable break generation function for transmitter - suppo rt s break detect function for receiver ? rs - 485 function mode. - suppo rt s rs - 485 9 - bit mode - supports hardware or software direct enable control provided by rts pin (uart0 and uart1 support)
n u m icro ? dec . 30 , 201 4 page 73 of 97 revision 1.0 1 numicro? 6.14 smart c ard host interface (sc) 6.14.1 overview the smart card interface controller (sc controller) is based on iso/iec 7816 - 3 standard and fully compliant with pc/sc specifications. it also provides status of card insertion/removal. it also support uart mode for f ull duplex asynchronous communications. 6.14.2 features ? support s up to t hree iso7816 - 3 ports (sc0, sc1 and sc2) - iso7816 - 3 t=0, t=1 compliant - emv2000 compliant - separate s receive / transmit 4 byte entry fifo for data payloads . - programmable transmission clock frequency . - programmable receiver buffer trigger level . - programmable guard time selection (11 etu ~ 26 7 etu) . - a 24 - bit and two 8 - bit time s for answer to request (atr) and waiting times processing . - support s auto inverse convention function . - support s transmitter and rec eiver error retry and error number limit ing function . - support s hardware activation sequence , hardware warm reset sequence and hardware deactivation sequence process. - support s hardware auto deactivation sequence when detect ing the card removal . ? supports up to three uart ports (uart3, uart4, uart5) - full duplex, asynchronous communications. - programmable data bit length , 5 - , 6 - , 7 - , 8 - bit character . - separate s receiving / transmitting 4 bytes entry fifo for data payloads. - support s programmable baud rate generator for each channel. - support s programmable receiver buffer trigger level. - programmable transmitting data delay time between the last stop bit leaving the tx - fifo and the de - assertion by setting scx_egtr [egt] register. - progra mmable even, odd or no parity bit generation and detection. - programmable stop bit, 1 or 2 stop bit generation .
n u m icro ? dec . 30 , 201 4 page 74 of 97 revision 1.0 1 numicro? 6.15 ps/2 device controller (ps2d) 6.15.1 overview ps/2 device controller provides a basic timing control for ps/2 communication. all communication between the device and the host is managed through the ps2_ clk and ps2_ data pins. unlike ps/2 keyboard or mouse device controller, the receive/transmit code needs to be translated as meaningful code by firmware. the device controller generates the ps2_ clk signal after receiving a r equest to s end state , but host has ultimate control over communication. data of ps2_ data line sent from the host to the device is read on the rising edge and sent from the device to the host is change after rising edge. a 16 bytes fifo is used to reduce cpu intervention. s oftware can select 1 to 16 bytes for a continuous transmission. 6.15.2 features ? host communication inhibit and "request - to - send" state detection ? reception frame error detection ? programmable 1 to 16 bytes transmit buffer to reduce cpu intervention ? double buffer for data reception ? s oftware override bus
n u m icro ? dec . 30 , 201 4 page 75 of 97 revision 1.0 1 numicro? 6.16 i 2 c serial interface controller (i 2 c) 6.16.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simpl e and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. 6.16.2 features the i 2 c bus uses two wires ( i2cn_ sda and i2cn_ scl) to transfer information between devices connected to the bus. the main features of the i 2 c bus include: ? supports up to two i 2 c serial interface controller ? master/slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allow devices with different bit rates to communicate via one serial bus ? built - in a 14 - bit time - out counter requesting the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows. ? programmable clocks allow for versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition ( four sl ave address with mask option) ? supports power - down wake - up function 6.17 serial peripheral interface (spi) 6.17.1 overview the serial peripheral interface (spi) is a synchronous serial data communication protocol that operates in full duplex mode. devices communicate i n m aster/ slave mode with the 4 - wire bi - direction interface. the numicro ? nuc230/240 series contains up to four sets of spi controller s performing a serial - to - parallel conversion on data received from a peripheral device, and a parallel - to - serial conversion on data transmitted to a peripheral device. each set of spi controller can be configured as a master or a slave device . th e spi contr oller supports the variable bus clock function for special application s and 2 - bit t ransfer mode to connect 2 off - chip slave devices at the same time. this controller also supports the pdma function to access the data buffer and also support s d ual i / o t rans fer mode.
n u m icro ? dec . 30 , 201 4 page 76 of 97 revision 1.0 1 numicro? 6.17.2 features ? up to four sets of spi controller s ? support s m aster or slave mode operation ? support s 2 - bit t ransfer mode ? support s d ual i / o t ransfer mode ? configurable bit length of a transaction word from 8 to 32 bit s ? provide s separate 8 - layer depth transmit and receive fifo buffers ? support s msb first or lsb first transfer sequence ? two slave select li nes in master mode ? support s the b yte r eorder function ? support s b yte or w ord s uspend mode ? variable output bus clock frequency in master mode ? support s pdma transfer ? support s 3 - wire, no slave select signal, bi - direction interface 6.18 i 2 s controller (i 2 s) 6.18.1 overview the i 2 s controller consists of i 2 s protocol to interface with external audio codec. two 8 - word dep th fifo for read ing path and writ ing path respectively and is capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes. p dma controller handles the data movement between fifo and memory. 6.18.2 features ? supports m aster mode and s lave mode ? capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes ? support s monaural and stereo audio data ? supports i 2 s and msb justified data format ? provides t wo 8 - word fifo data buffers, one for transmit ting and the other for receiv ing ? supports p dma transfer
n u m icro ? dec . 30 , 201 4 page 77 of 97 revision 1.0 1 numicro? 6.19 usb device controller (usb d ) 6.19.1 overview there is one set of usb 2.0 full - speed device controller and transceiver in this device. it is compliant with usb 2.0 full - speed device specification and support s control/bulk/interrupt/ isochronous transfer types. in this device controller, there are two main interfaces: the apb bus and usb bus which comes from the usb phy transceiver. for the apb bus, the cpu can program control registers through it. there are 512 bytes internal sram as data buffer in this controller. for in or out transfer, it is necessary to write data to sram or read data from sram through the apb interface or sie. user needs to set the effective starting address of sram for each endpoint buffer through buffer segmentation register (usb_bufsegx). there are 8 endpoints in this controller. each of the endpoint can be configured as in or out endpoint. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. the block of e ndpoint c ontrol is also used to manage the data sequential synchronization, endpoint states, current start address, transaction status, and data buffer status for each endpoint. there are four different interrupt events in this controller. they are the wake - up function, device plug - in or plug - out event, usb events, and bus events. any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register (usb_intsts) to acknowledge what kind of interrupt occurring, and then check the related usb endpoint status register (usb_epsts) to acknowledge wha t kind of event occurring in this endpoint. a software - dis connect function is also supported for this usb controller. it is used to simulate the disconnection of this device from the host. if drvse0 (usb_drvse0 [0] ) is set to 1 , the usb controller will force the output of usb_d + and usb_d - to level low. after drvse0 bit is cleared to 0 , host will enumerate the usb device again. please refer to universal serial bus specification revision 1.1 for details. 6.19.2 features ? compliant with usb 2.0 full - speed s pecification ? provide s 1 interrupt vector with 4 different interrupt events (wakeup, fldet, usb and bus) ? support s control/bulk/interrupt/isochronous transfer type ? support s suspend function when no bus activity existing for 3 ms ? provide s 8 endpoints for conf igurable control/bulk/interrupt/isochronous transfer types and maximum 512 bytes buffer size ? provide s remote wake - up capability
n u m icro ? dec . 30 , 201 4 page 78 of 97 revision 1.0 1 numicro? 6.20 controller area network (can) 6.20.1 overview the c_can consists of the can core, message ram, message handler, control registers and module interface (refer e` ! ??? ). the can core performs communication according to the can protocol version 2.0 part a and b. the bit rate can be programmed to values up to 1mbit/s. for the connection to the physical layer, additional transceiver hardware is required. for communication on a can network, individual message objects are configured. the message objects and identifier masks for acceptan ce filtering of received messages are stored in the message ram. all functions concerning the handling of messages are implemented in the message handler. these functions include acceptance filtering, the transfer of messages between the can core and the m essage ram, and the handling of transmission requests as well as the generation of the module interrupt. the register set of the c_can can be accessed directly by the software through the module interface. these registers are used to control/configure the can core and the message handler and to access the message ram. 6.20.2 features ? supports can protocol version 2.0 part a and b. ? bit rates up to 1 mbit/s. ? 32 message objects. ? each message object has its own identifier mask. ? programmable fifo mode (concatenation o f message objects). ? maskable interrupt. ? disabled automatic re - transmission mode for time triggered can applications. ? programmable loop - back mode for self - test operation. ? 16 - bit module interfaces to the amba apb bus. ? support s wake - up function 6.21 analog - to - digital converter (adc) 6.21.1 overview the numicro ? nuc230/240 s eries contains one 12 - bit successive approximation analog - to - digital converters (sar a/d converter) with 8 input channels. the a/d converter supports three operation modes: single, single - cycle scan and continuous scan mode. the a/d converter can be started by software, pwm c enter - aligned trigger and external stadc pin. 6.21.2 features ? a nalog input voltage range: 0~vref ? 12 - bit resolution and 10 - bit accuracy is guaranteed ? up to 8 single - end analog input channels or 4 differential analog input channels
n u m icro ? dec . 30 , 201 4 page 79 of 97 revision 1.0 1 numicro? ? up to 1 msps conversion rate (chip working at 5v) ? three operating modes - single mode: a/d conversion is performed one time on a specified channel - single - cycle scan mode: a/d conversion is performed one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel - continuous scan mode: a/d converter continuously performs single - cycle scan mode until software stops a/d conversion ? an a/d conversion can be started by: - writing 1 to adst bit (adcr[11])through software - pwm center - aligned trigger - external pin stadc ? conversion results are held in data registers for each channel with valid and overrun indicators ? supports two set digital comparators. the c onvers ion result can be compared with specify value and user can select whether to generate an interrupt when conversion result matches the compare register setting ? channel 7 supports 3 input sources: external analog voltage, internal band - gap voltage, and inter nal temperature sensor output 6.22 analog comparator ( a cmp) 6.22.1 overview the numicro ? nuc230/240 s eries contains two comparators which can be used in a number of different configurations. the comparator output is logic 1 when positive input voltage is greater than negative input voltage ; otherwise the output is logic 0 . each comparator can be configured to generate interrupt request when the comparator output value changes. the block diagram is shown in e` ! ??? . 6.22.2 features ? analog input voltage range: 0~ v dda (voltage of av dd pin) ? supports hysteresis function ? o ptional internal reference voltage source for each comparator negative input
n u m icro ? dec . 30 , 201 4 page 80 of 97 revision 1.0 1 numicro? 7 application circuit a v s s a v d d a v c c d v c c v s s v d d 4 ~ 2 4 m h z c r y s t a l 0 . 1 u f f b f b 2 0 p 2 0 p d v c c 1 0 u f / 2 5 v 1 0 k p o w e r c r y s t a l r e s e t c i r c u i t n r s t x t a l 2 l d o _ c a p n u c 2 x x s e r i e s v d d v s s n r s t i c e _ c l k i c e _ d a t s w d i n t e r f a c e 1 u f v d d v s s i 2 c d e v i c e c l k d i o s d a 0 s c l 0 4 . 7 k v d d v s s s p i d e v i c e c s c l k m i s o s p i s s 0 m o s i s p i c l k 0 m i s o _ 0 m o s i _ 0 l d o r s 2 3 2 t r a n s c e i v e r r o u t t i n r i n t o u t p c c o m p o r t x t a l 1 0 . 1 u f d v c c 4 . 7 k d v c c d v c c n o t e : f o r t h e s p i d e v i c e , t h e c h i p s u p p l y v o l t a g e m u s t b e e q u a l t o s p i d e v i c e w o r k i n g v o l t a g e . f o r e x a m p l e , w h e n t h e s p i f l a s h w o r k i n g v o l t a g e i s 3 . 3 v , t h e m 0 5 x x c h i p s u p p l y v o l t a g e m u s t a l s o b e 3 . 3 v . u a r t [ 1 ] r x d t x d c a n t r a n s c e i v e r r c a n _ h c a n _ l o d b p o r t c a n c a n _ t x c a n _ r x d s m a r t c a r d v c c s m a r t c a r d s l o t s c _ p w r s c _ r s t s c _ c l k s c _ d a t s c _ d e t e c t
n u m icro ? dec . 30 , 201 4 page 81 of 97 revision 1.0 1 numicro? 8 electrical characte r istics 8.1 absolute maximum ratings symbol parameter min . max unit dc power supply v dd ? v ss - 0.3 +7.0 v battery power supply v bat +2.4 +5.0 v input voltage v in v ss - 0.3 v dd +0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature t a - 40 + 105 ? c storage temperature t st - 55 +150 ? c maximum current into v dd - 120 ma maximum current out of v ss 120 ma maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
n u m icro ? dec . 30 , 201 4 page 82 of 97 revision 1.0 1 numicro? 8.2 dc electrical characteristics (v dd - v ss = 5.5 v, t a = 25 ? c, f osc = 50 mhz unless otherwise specified.) parameter sym . specification test conditions min. typ. max. unit operation v oltage v dd 2.5 5.5 v v dd = 2.5v ~ 5.5v up to 72 mhz power ground v ss av ss - 0.3 v ldo output voltage v ldo 1.62 1.8 1.98 v v dd > 2. 5 v band - gap voltage v bg 1.22 1.25 1.28 v v dd = 2 .5 v ~ 5.5 v , t a = 25 ? dd v dd v when system used analog function, please refer to nuc230/240 series technical reference manual chapter 6.5 for corresponding analog operating voltage rtc operating voltage v bat 2.5 5.5 v operating current normal run mode at 72 mhz while(1){} executed from flash v ldo =1.8 v i dd1 50 ma v dd hxt hirc pll all digital module 5.5v 12 mhz x v v i dd2 20 ma 5.5v 12 mhz x v x i dd3 48 ma 3.3v 12 mhz x v v i dd4 1 8 ma 3.3v 12 mhz x v x operating current normal run mode at 50 mhz while(1){} executed from flash v ldo =1.8 v i dd 5 34 ma 5.5v 12 mhz x v v i dd 6 15 ma 5.5v 12 mhz x v x i dd 7 32 ma 3.3v 12 mhz x v v i dd 8 14 ma 3.3v 12 mhz x v x operating current normal run mode at 12 mhz while(1){} executed from flash v ldo =1.8 v i dd 9 8.5 ma 5.5v 12 mhz x x v i dd 10 3.6 ma 5.5v 12 mhz x x x i dd 11 7.5 ma 3.3v 12 mhz x x v i dd 12 2.6 ma 3.3v 12 mhz x x x operating current normal run mode at 4 mhz while(1){} executed from flash v ldo =1.8 v i dd 13 3.6 ma 5.5v 4 mhz x x v i dd 14 2 ma 5.5v 4 mhz x x x i dd1 5 2.8 ma 3.3v 4 mhz x x v i dd1 6 1.2 ma 3.3v 4 mhz x x x
n u m icro ? dec . 30 , 201 4 page 83 of 97 revision 1.0 1 numicro? parameter sym . specification test conditions min. typ. max. unit operating current normal run mode at 32.768 khz while(1){} executed from flash v ldo =1.8 v i dd1 7 141 ? a v dd lxt (khz) hirc pll all digital module 5.5v 32.768 x x v i dd1 8 129 ? a 5.5v 32.768 x x x i dd1 9 138 ? a 3.3v 32.768 x x v i dd 20 125 ? a 3.3v 32.768 x x x operating current normal run mode at 10 khz while(1){} executed from flash v ldo =1.8 v i dd 21 125 ? a v dd hxt/lxt lirc (khz) pll all digital module 5.5v x 10 x v i dd 22 120 ? a 5.5v x 10 x x i dd 23 125 ? a 3.3v x 10 x v i dd 24 120 ? a 3.3v x 10 x x operating current idle mode at 72 mhz v ldo =1.8 v i idle1 42 ma v dd hxt hirc pll all digital module 5.5v 12 mhz x v v i idle2 1 1 ma 5.5v 12 mhz x v x i idle3 41 ma 3.3v 12 mhz x v v i idle4 9 ma 3.3v 12 mhz x v x operating current idle mode at 50 mhz v ldo =1.8 v i idle 5 28 ma 5.5v 12 mhz x v v i idle 6 10 ma 5.5v 12 mhz x v x i idle 7 27 ma 3.3v 12 mhz x v v i idle 8 9 ma 3.3v 12 mhz x v x operating current idle mode at 12 mhz v ldo =1.8 v i idle 9 7.5 ma 5.5v 12 mhz x x v i idle 10 2.4 ma 5.5v 12 mhz x x x i idle 11 6.5 ma 3.3v 12 mhz x x v i idle 12 1.5 ma 3.3v 12 mhz x x x operating current idle mode at 4 mhz v ldo =1.8 v i idle 13 3.3 ma 5.5v 4 mhz x x v i idle1 4 1.7 ma 5.5v 4 mhz x x x i idle1 5 2.4 ma 3.3v 4 mhz x x v i idle1 6 0.8 ma 3.3v 4 mhz x x x operating current idle mode at 32.768 k hz v ldo =1.8 v i idle 1 7 133 ? a v dd lxt (khz) hirc pll all digital module 5.5v 32.768 x x v i idle1 8 120 ? a 5.5v 32.768 x x x
n u m icro ? dec . 30 , 201 4 page 84 of 97 revision 1.0 1 numicro? parameter sym . specification test conditions min. typ. max. unit i idle1 9 133 ? a 3.3v 32.768 x x v i idle 20 120 ? a 3.3v 32.768 x x x operating current idle mode at 10 k hz i idle 2 1 122 ? a v dd hxt/lxt lirc (khz) pll all digital module 5.5v x 10 x v i idle 22 118 ? a 5.5v x 10 x x i idle 23 122 ? a 3.3v x 10 x v i idle 24 118 ? a 3.3v x 10 x x standby current power - down mode (deep sleep mode) v ldo =1.6 v i pwd1 15 ? a v dd hxt/hirc pll lxt (khz) rtc ram retension 5.5v x x x v i pwd 2 15 ? a 5.5v x x x v i pwd 3 17 ? a 3.3v x 32.768 v v i pwd 4 17 ? a 3.3v x 32.768 v v rtc operating current i vbat 1.6 ? a v bat = 3.0v, rtc enabled input current pa, pb, pc, pd, pe , pf (quasi - bidirectional mode) i in1 - 50 - 60 ? a v dd = 5.5v, v in = 0v or v in =v dd input current at /reset [1] i in2 - 55 - 45 - 30 ? a v dd = 3.3v, v in = 0.45v input leakage current pa, pb, pc, pd, pe , pf i lk - 2 - + 2 ? a v dd = 5.5v, 0 n u m icro ? dec . 30 , 201 4 page 85 of 97 revision 1.0 1 numicro? parameter sym . specification test conditions min. typ. max. unit hysteresis voltage of pa , pb, pc, pd,pe, pf (schmitt input) v hy 0.2v dd v input low voltage xt1 _in [*2] v il3 0 - 0.8 v v dd = 4.5v 0 - 0.4 v dd = 3.0v input high voltage xt1 _in [*2] v ih3 3.5 - v dd +0.2 v v dd = 5.5v 2.4 - v dd +0.2 v dd = 3.0v input low voltage x32i [*2] v il 4 0 - 0.4 v input high voltage x32i [*2] v ih 4 1.2 1.8 v negative going threshold (schmitt input), /reset v ils - 0.5 - 0. 2 v dd - 0. 2 v positive going threshold (schmitt input), /reset v ihs 0.7v dd - v dd +0.5 v source current pa, pb, pc, pd, pe , pf (quasi - b idirectional mode) i sr11 - 30 0 - 37 0 - 45 0 ? a v dd = 4.5v, v s = 2.4v i sr12 - 50 - 7 0 - 9 0 ? a v dd = 2.7v, v s = 2.2v i sr12 - 40 - 60 - 80 ? a v dd = 2.5v, v s = 2.0v source current pa, pb, pc, pd, pe , pf (push - pull mode) i sr21 - 24 - 28 - 32 ma v dd = 4.5v, v s = 2.4v i sr22 - 4 - 6 - 8 ma v dd = 2.7v, v s = 2.2v i sr22 - 3 - 5 - 7 ma v dd = 2.5v, v s = 2.0v sink current pa, pb, pc, pd, pe , pf (quasi - bidirectional and push - pull mode) i sk1 10 16 20 ma v dd = 4.5v, v s = 0.45v i sk1 7 10 13 ma v dd = 2.7v, v s = 0.45v i sk1 6 9 12 ma v dd = 2.5v, v s = 0.45v brown - out v oltage with bo d _vl [1:0] = 00b v bo2. 2 2. 1 2. 2 2. 3 v brown - out v oltage with bo d _vl [1:0] = 01b v bo2. 7 2.6 2.7 2.8 v brown - out voltage with bo d _vl [1:0] = 10b v bo3. 7 3. 5 3. 7 3. 9 v brown - out v oltage with bo d _vl [1:0] = 11b v bo4. 4 4. 2 4. 4 4. 6 v
n u m icro ? dec . 30 , 201 4 page 86 of 97 revision 1.0 1 numicro? parameter sym . specification test conditions min. typ. max. unit hysteresis range of bod voltage v b h 30 - 1 5 0 mv v dd = 2.5v~5.5v note: 1. /reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. pins of pa, pb, pc, pd , pe and p f can source a transition current when they are being ex ternally driven from 1 to 0. in the condition of v dd = 5.5 v, t he transition current reaches its maximum value when v in approximates to 2 v.
n u m icro ? dec . 30 , 201 4 page 87 of 97 revision 1.0 1 numicro? 8.3 ac electrical characteristics 8.3.1 external 4~24 mhz high speed oscillator note: duty cycle is 50%. symbol parameter condition min . typ . max . unit t chcx clock high time 1 0 - - ns t clcx clock low time 1 0 - - ns t clch clock rise time 2 - 1 5 ns t chcl clock fall time 2 - 1 5 ns 8.3.2 external 4~24 mhz high speed crystal parameter condition min . typ . . max . unit operation voltage v dd - 2. 5 - 5.5 v temperature - - 40 - 105 operating c urrent 12 mhz at v dd = 5v - 2 - ma c lock f requency external crystal 4 24 mhz 8.3.2.1 typical crystal application circuits crystal c1 c2 r 4 mhz ~ 24 mhz 10~20pf 10~20pf without t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l 0 . 3 v d d 0 . 7 v d d
n u m icro ? dec . 30 , 201 4 page 88 of 97 revision 1.0 1 numicro? figure 8 - 1 typical crystal application circuit 8.3.3 external 32.768 khz low speed crystal oscillator parameter condition min . typ . max . unit operation voltage v dd - 2. 5 - 5.5 v operation temperature - - 40 - 105 operation current 32.768khz at v dd =5v 1.6 ? a c lock f requency external crystal - 32 .768 - khz 8.3.4 internal 22.1184 mhz high speed oscillator parameter condition min . typ . max . unit operation voltage v dd - 2.5 - 5.5 v center frequency - - 22.1184 - mhz calibrated internal oscillator frequency +25 ; v dd =5 v - 1 - +1 % - 40 ~+ 105 ; v dd =2.5 v~5.5 v - 3 - +3 % operation current v dd =5 v - 8 00 - ua 8.3.5 internal 10 khz low speed oscillator parameter condition min . typ . max . unit operation voltage v dd - 2.5 - 5.5 v center frequency - - 10 - khz calibrated internal oscillator frequency +25 ; v dd =5 v - 2 0 - + 2 0 % - 40 ~+ 105 ; v dd =2.5 v~5.5 v - 50 - +50 % x t 1 _ i n x t 1 _ o u t c 1 r c 2
n u m icro ? dec . 30 , 201 4 page 89 of 97 revision 1.0 1 numicro? 8.4 analog characteristics 8.4.1 12 - bit saradc specification symbol parameter min . typ . max . unit - resolution - - 12 bit dnl differential nonlinearity error - - 1~2 - 1~4 lsb inl integral nonlinearity error - 2 4 lsb eo offset error - 2 4 lsb eg gain error (transfer gain) - - 2 - 4 - - monotonic guaranteed f adc adc clock frequency (av dd = 5v/3v) - - 16/8 mhz f s sample rate - - 1 m sps v dd a supply voltage 3 - 5.5 v i dda supply current (avg.) 2.9 ma v ref reference voltage 3 v dd a v v in input voltage 0 - v ref v 8.4.2 ldo and power m anagement specification parameter min . typ . max . unit note input voltage v dd 2. 5 5.5 v v dd input voltage output voltage 1.62 1.8 1.98 v v dd > 2.5 v operating temperature - 40 25 105 cbp - 1 - ? f r esr = 1 ? note: 1. it is recommended that a 10 uf or higher capacitor and a 100 nf bypass capacitor are connected between v dd and the closest v ss pin of the device. 2. to ensur e power stability, a n 1 ? f or higher capacitor must be connected between ldo _cap pin and the closest v ss pin of the device.
n u m icro ? dec . 30 , 201 4 page 90 of 97 revision 1.0 1 numicro? 8.4.3 low voltage reset specification parameter condition min . typ . max . unit operation v oltage - 0 - 5.5 v quiescent c urrent a v dd =5.5 v - 1 5 ? a operation t emperature - - 40 25 105 threshold v oltage - 1. 6 2.0 2. 4 v hysteresis - 0 0 0 v 8.4.4 brown - out detector specification parameter condition min . typ . max . unit operation v oltage - 0 - 5.5 v temperature - - 40 25 105 quiescent c urrent av dd =5.5 v - - 125 a brown - out v oltage bo d _vl [1:0]=11 4. 2 4. 4 4.6 v bo d _vl [1:0]=10 3. 5 3. 7 3.9 v bo d _vl [1:0]=01 2.6 2.7 2.8 v bo d _vl [1:0]=00 2. 1 2. 2 2. 3 v hysteresis - 30 - 150 mv 8.4.5 power - o n reset specification parameter condition min . typ . max . unit operation temperature - - 40 25 105 reset v oltage v+ - 2 - v quiescent c urrent vin > reset voltage - 1 - na
n u m icro ? dec . 30 , 201 4 page 91 of 97 revision 1.0 1 numicro? 8.4.6 temperature sensor specification parameter conditions min . typ . max . unit operation v oltage [1] 2.5 - 5.5 v operation t emperature - 40 - 105 current c onsumption 16 a gain - 1.55 - 1.65 - 1.75 mv/ offset voltage temp=0 735 745 755 mv note: internal operation voltage comes from internal ldo. 8.4.7 comparator specification parameter condition min . typ . max . unit operation voltage a v dd - 2. 5 5.5 v operation temperature - - 40 25 105 operation c urrent v dd =3 .0 v - 20 40 a input o ffset v oltage - - 10 20 mv output s wing - 0.1 - v dd - 0.1 v input c ommon m ode r ange - 0.1 - v dd - 1.2 v dc g ain - - 70 - db propagation d elay vcm=1.2 v and vdiff=0.1 v - 200 - ns comparison v oltage 20 mv at vcm=1 v 50 mv at vcm=0.1 v 50 mv at vcm=v dd - 1.2 10 mv for non - hysteresis 10 20 - mv hysteresis vcm=0.4 v ~ v dd - 1.2 v - 10 - mv wake - up t ime cinp=1.3 v cinn=1.2 v - - 2 s
n u m icro ? dec . 30 , 201 4 page 92 of 97 revision 1.0 1 numicro? 8.4.8 usb phy specification 8.4.8.1 usb dc electrical characteristics symbol parameter conditions min . typ . max . unit v ih input h igh (driven) 2.0 v v il input l ow 0.8 v v di differential i nput s ensitivity |padp - padm| 0.2 v v cm differential c ommon - mode r ange includes v di range 0.8 2.5 v v se single - ended r eceiver t hreshold 0.8 2.0 v receiver h ysteresis 200 mv v ol output l ow (driven) 0 0.3 v v oh output h igh (driven) 2.8 3.6 v v crs output s ignal c ross v oltage 1.3 2.0 v r pu pull - up r esistor 1.425 1.575 k v trm termination voltage for u pstream p ort p ull - up (rpu) 3.0 3.6 v z drv driver o utput r esistance steady state drive* 10 c in transceiver c apacitance pin to gnd 20 pf *driver output resistance doesnt include series resistor resistance. 8.4.8.2 usb full - speed driver electrical characteristics symbol parameter conditions min . typ . max . unit t fr rise time c l =50p 4 20 ns t ff fall time c l =50p 4 20 ns t frff rise and f all t ime m atching t frff =t fr /t ff 90 111.11 % 8.4.8.3 usb power dissipation symbol parameter conditions min . typ . max . unit i v bus v bus current (steady state) standby 50 a
n u m icro ? dec . 30 , 201 4 page 93 of 97 revision 1.0 1 numicro? 8.4.8.4 usb ldo specification symbol parameter conditions min . typ . max . unit v bus vbus pin input voltage 4.0 5.0 5.5 v v dd33 ldo output voltage 3.0 3.3 3.6 v c bp external bypass capacitor 1.0 - uf 8.5 flash dc electrical characteristics symbol parameter conditions min . typ . max . unit v dd supply voltage 1.62 1.8 1.98 v [2] n endur endurance 10000 cycles [1] t ret data retention at 25 100 year t erase page erase time 20 ms t mer mass erase time 40 ms t prog program time 40 s i dd 1 read current - 0.15 0.5 ma/mhz i dd 2 program/erase current 7 ma 1. number of program/erase cycles. 2. v dd is source from chip ldo output voltage. this table is guaranteed by design, not test in production.
n u m icro ? dec . 30 , 201 4 page 94 of 97 revision 1.0 1 numicro? 9 package dimensions 9.1 100 - pin lqfp (14x14x1.4 mm footprint 2.0 mm) controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.50 14.10 0.20 0.27 1.45 1.60 14.00 1.40 13.90 0.10 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.055 0.020 0.556 0.551 0.547 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a1 a 2 l1 e 0.009 0.006 0.15 0.22 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 ? 0.638 0.630 0.622 d d e e b a2 a1 a l1 e c l y h h 1 100 ? 25 26 50 51 7 5 7 6
n u m icro ? dec . 30 , 201 4 page 95 of 97 revision 1.0 1 numicro? 9.2 64 - pin lqfp ( 7 x 7 x1.4 mm footprint 2.0 mm)
n u m icro ? dec . 30 , 201 4 page 96 of 97 revision 1.0 1 numicro? 9.3 48 - pin lqfp (7x7x1.4 mm footprint 2.0 mm) 1 12 48 h h ? controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
n u m icro ? dec . 30 , 201 4 page 97 of 97 revision 1.0 1 numicro? 10 revision history r e vi sion date description 1 .0 0 may 1 2 , 201 4 preliminary version 1.01 dec . 30 ,2014 1, added ebi function 2, rearranged the chepter sequence. important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed , insecure usage. insecure usage includes, but is no t limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of saf ety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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